Abstract: A display device which can suppress erroneous display of a display panel is provided. A source driver receives a serial data signal in which a preamble and video data of the display panel are alternately continuous via an interface from a display controller. The source driver controls timing of supply of a gate signal from a gate driver based on the video data included in the serial data signal, and supplies a gradation voltage signal which corresponds to the video data to a plurality of data lines of the display panel. The source driver has a detection portion which detects that the interface is in an unstable state, and a gate reset signal output portion which outputs a gate reset signal for stopping an operation of the gate driver when the unstable state of the interface is detected at the time of the supply of the video data.

Abstract: A current corresponding to the difference between an input signal voltage and an output signal voltage is generated as an amplification acceleration current. The amplification acceleration current is sent to an output node of a current mirror, which drives a transistor in an output amplifier stage, and therefore added to a current to drive the transistor in the output amplifier stage.

Abstract: A semiconductor device and a method of generating a power on reset signal that can reliably perform power on reset on an internal circuit and subsequently cancel the reset state regardless of environmental temperature are provided. The semiconductor device according to the disclosure includes: a voltage divider circuit dividing a power supply voltage to obtain first and second voltages having different voltage values; a first transistor receiving the first voltage at the control electrode to generate a first current; a second transistor receiving the second voltage at the control electrode to generate a second current; a current comparing part comparing the first and second currents to generate a current comparison result signal representing a comparison result; and a reset signal generating part generating a power on reset signal having a first level that prompts reset or a second level that prompts reset cancelation based on the current comparison result signal.

Abstract: An offset calculation device includes a determination unit configured to determine a rotation state of an object having an angular velocity sensed by a gyro sensor based on a moving average value of sensed angular velocity during a plurality of time periods differing from each other, the moving average value being calculated from chronological data of numerical values corresponding to the sensor data output from the gyro sensor. The offset calculation device further includes a calculation unit configured to calculate an offset value of the sensor data based on the sensor data corresponding to a time period in which the target object was deemed to be in a non-rotation state by the determination unit.

Abstract: A capacitance sensor circuit is provided, including: a capacitance variable capacitor changing from a first capacitance to a second capacitance corresponding to environmental change; a reference capacitor; and an amplifier circuit charging the capacitance variable capacitor via a first node and the reference capacitor via a second node, and outputting a determination signal. In the amplifier circuit, a differential amplification part generates a potential difference signal obtained by amplifying the potential difference between the first and the second nodes; an output part outputs the determination signal based on the potential difference signal; and when the difference between the increase degrees of the potentials of the first and the second nodes is less than a predetermined value, the output part holds and outputs the determination signal immediately before that state and a bias control part stops a current flowing through the differential amplification part.

Abstract: Provided is a semiconductor device including a regulator that generates a first voltage and applying the first voltage to a first line; an external terminal that is connected to the first line and externally connects an external component; and a test circuit that inspects a connection state of the external component. The test circuit includes a test discharge execution unit that is configured, upon receiving a test start signal, to stop the operation of the regulator and discharge the external component by connecting the first line to a predetermined potential; and a discharge duration measurement unit that measures a time required from the reception of the test start signal to a drop of the voltage of the first line below a predetermined second voltage, as a discharge duration of the component, and generate discharge duration information about the discharge duration.

Abstract: A flag retaining circuit comprises a first capacitor element having one end connected to a first line and the other end grounded; a flag setting unit that charges the first capacitor element according to an input signal; a flag checking unit that outputs 0 or 1 based on the potential of the first capacitor element; and a discharging unit that discharges the first capacitor element. The discharging unit includes a transconductance element that discharges the first capacitor element via the first line; a control switch that receives supply of the voltage on a second line; and a second capacitor element having one end connected to a node between a control input end of the transconductance element and the control switch, and the other end grounded. The flag checking unit outputs the inverse of the voltage on the first line onto the second line.

Abstract: A data slicer for converting an envelope signal of an amplitude-modulated wave into a binary signal, comprises: an average level generation circuit configured to generate an average level of the envelope signal by averaging the envelope signal per time; a fixed voltage value generation circuit configured to generate a fixed voltage value; a reference level generation circuit configured to generate a reference level in accordance with the fixed voltage value and the average level of the envelope signal; and a comparison circuit configured to compare a signal level of the envelope signal with the reference level to output a result of the comparison as the binary signal.

Abstract: A semiconductor device includes insulating substrate; a compound semiconductor layer provided in a first region of a surface of the insulating substrate; and a silicon layer provided in a second region, differing from the first region, of the surface of the insulating substrate. The semiconductor device further includes: a first gate electrode provided on a surface of the compound semiconductor layer; a pair of conductive members provided at positions on the surface of the compound semiconductor layer to sandwich the first gate electrode between the pair of conductive members; a second gate electrode provided on a surface of the silicon layer; and a pair of diffusion layers provided at positions in the silicon layer to sandwich the second gate electrode between the pair of diffusion layers. One of the conductive members is electrically connected to one of the diffusion layers.

Abstract: A semiconductor device of a peripheral device control system includes one or more management blocks that are provided in association with a device to be controlled. The management blocks each include a plurality of registers that store information pertaining to each operation of the device to be controlled, and a first generation unit that performs a predetermined aggregation process on values of the plurality of registers included in the management block to generate an aggregation value that is a value formed by aggregating the values of the plurality of registers.

Abstract: The disclosure provides a wireless power supply device, which includes: a power transmission coil; a first driving unit that alternatively performs an operation of transmitting a first driving current to one end of the power transmission coil and an operation of drawing a second driving current away from one end of the power transmission coil; a second driving unit that alternatively performs an operation of transmitting the second driving current to the other end of the power transmission coil and an operation of drawing the first driving current away from the other end of the power transmission coil; a current detection unit that detects amounts of the transmitted first and second driving current to generate a first signal, and detects an amount of the drawn second driving current to generate a second signal; and a control unit that determines an operation state based on the first and second signal.

Abstract: A semiconductor memory device includes: a first bit line; a second bit line connected to the first bit line via a first switch; a charge transfer section including: a first holding section connected to the second bit line, the first holding section being configured to hold a readout voltage from a memory section that stores data, and a second holding section connected to the first bit line, the second holding section being configured to hold a voltage generated due to transfer of charges between the first holding section and the second holding section, the charge transfer section being configured to transfer charges between the first holding section and the second holding section via the first bit line; and a comparison section configured to compare a voltage held in the second holding section with a reference voltage.

Abstract: A method for writing data includes: data maintaining step for maintaining writing object data to each of a plurality of memory devices; obtaining step for obtaining identification information assigned to each of the plurality of memory devices; generating step for generating combination data by associating and combining the identification information and the writing object data with respect to the plurality of memory devices; and sending step for sending the combination data to the plurality of memory devices; which are performed by a writing device. The method also includes receiving step for receiving the combination data; extracting step for extracting the writing object data corresponding to the memory device on the basis of the identification information from the combination data; and memorizing step for memorizing the target data for writing extracted from the combination data; which are performed by each of the plurality of memory devices.

Abstract: A semiconductor device including a resistance section that includes a first terminal and a second terminal disposed in contact with an outer periphery, and a serial resistance section in which plural resistance elements are connected in series, wherein one end of the serial resistance section is connected to the first terminal, and another end of the serial resistance section is connected to the second terminal; and a current adjustment section that includes a current source that supplies current to the serial resistance section, and disposed adjacent to the resistance section such that a distance between the first terminal and the current adjustment section along the outer periphery of the resistance section and a distance between the second terminal and the current adjustment section along the outer periphery of the resistance section are equal.

Abstract: A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction; a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components.

Abstract: A failure determination device allows a user to define conditions indicating a failure of the device. The failure determination device includes a difference detector configured to output a difference detection signal that indicates a difference between an input signal and an output signal output from a processor that performs a prescribed process on the input signal and a determination unit configured to output a determination signal indicating a determination result on presence or absence of a failure in the processor, based on the difference detection signal. A level detector outputs a level detection signal indicating whether a level of the input signal is within a prescribed range. The determination unit updates the determination signal when the level detection signal indicates that the level of the input signal is within the prescribed range, and stops updating the determination signal when the level detection signal indicates that the level of the input signal is not within the prescribed range.

Abstract: A semiconductor device is provided, the device including a first detection section having a removal section to remove DC offset components included in each of an input signal and an output signal output from an amplification section that amplifies the input signal, and a correction section configured to perform correction to match phases of the input signal and the output signal from which the DC offset components have been removed, and to match gains of the input signal and of the output signal, the first detection section comparing a waveform of the input signal to a waveform of the output signal, and a second detection section to detect a mismatch between the DC offset component included in the input signal that is input into the removal section and the DC offset component included in the output signal that is input into the removal section.

Abstract: A semiconductor device and a method of generating a power-on reset signal are provided. The semiconductor device includes a regulator configured to generate a regulated power supply voltage having a lower voltage value than a power supply voltage based on the power supply voltage and output the regulated power supply voltage to an internal power supply line, and a power-on reset circuit configured to generate a signal which has a first level at which reset is prompted immediately after power for the power supply voltage is turned on and which transitions to a second level at which reset release is prompted from the first level when a voltage value of the internal power supply line has risen as a power-on reset signal.

Abstract: A semiconductor device including: a substrate including, in a central portion the substrate, n first element formation regions having a rectangular shape and arrayed along a first direction, and n+m second element formation regions arrayed along the first direction adjacent to the first element formation regions; plural projecting electrodes formed at each of the first and the second element formation regions; and plural dummy projecting electrodes formed, at a peripheral portion, overlapping a triangle defined by a first edge of the first element formation region that forms a boundary between the first element formation region and the peripheral portion, and a second edge of the second element formation region that is adjacent to a corner of the first edge and that forms a boundary between the second element formation region and the peripheral portion.

Abstract: An output circuit includes a differential amplifier including an inverting input terminal, non-inverting input terminals and an output terminal, and outputs, from the output terminal, a voltage having a level corresponding to a weighted average of respective input voltage levels of the non-inverting input terminals, when the output voltage level is equal to a input voltage level of the inverting input terminal, and outputs a voltage having a level corresponding to a difference between a level corresponding to a weighted average of the respective input voltage levels of the non-inverting input terminals and the input voltage level, when which the output voltage level is different from the input voltage level; and a delay circuit that generates a delay voltage responding with a predetermined time constant with respect to a change in the output voltage level and supplies the delay voltage to the inverting input terminal.