Abstract: A semiconductor device, a non-contact electronic device, and a period detection method are provided. The semiconductor device includes an edge detection unit that detects edges of one of rises and falls of a data signal received via radio waves, a counting unit that counts a number of N-divided clock signals having a frequency which is 1/N (N is an integer equal to or greater than 2) of a frequency of a reference clock signal having a predetermined frequency according to the data signal in a section of the adjacent edges, a fraction counting unit that counts fractions of the N-divided clock signals determined according to a phase difference between the edge and the N-divided clock signal, and a first addition unit that adds a value obtained by multiplying the counted number by N to the fractions, and outputs a resultant value as a period of the data signal.

Abstract: A failure determination device allows a user to define conditions indicating a failure of the device. The failure determination device includes a difference detector configured to output a difference detection signal that indicates a difference between an input signal and an output signal output from a processor that performs a prescribed process on the input signal and a determination unit configured to output a determination signal indicating a determination result on presence or absence of a failure in the processor, based on the difference detection signal. A level detector outputs a level detection signal indicating whether a level of the input signal is within a prescribed range. The determination unit updates the determination signal when the level detection signal indicates that the level of the input signal is within the prescribed range, and stops updating the determination signal when the level detection signal indicates that the level of the input signal is not within the prescribed range.

Abstract: A method of fabricating a semiconductor device includes forming a first semiconductor region at a front surface of a substrate, the first semiconductor region including an active element that regulates current flowing in a thickness direction of the substrate; grinding a rear surface of the substrate; after the grinding, performing a first etching that etches the rear surface of the substrate with a chemical solution including phosphorus; after the first etching, performing a second etching that etches the rear surface with an etching method with a lower etching rate than the first etching; and after the second etching, forming a second semiconductor region through which the current is to flow, by implanting impurities from the rear surface of the substrate.

Abstract: There is provided a measurement device including: a first electrode and a second electrode that are configured to form an energization path via a measurement object at a front side and measure an electrical conductivity of the measurement object; and a reference electrode and an ISFET that are configured to measure a pH value of the measurement object, wherein a standard electrode of the reference electrode is disposed at a rear side of the first electrode and the second electrode.

Abstract: In the present invention, a differential amplifier that includes a first output transistor and a second output transistor includes a boost circuit that includes a third output transistor and a fourth output transistor. The first output transistor delivers a current according to a first differential signal generated in a differential stage to an output terminal. The second output transistor extracts a current according to a second differential signal generated as a signal which is the same phase with a different potential of the first differential signal from the output terminal. The third output transistor delivers a current to the output terminal according to a level-shifting signal generated by level-shifting the first differential signal. The fourth output transistor extracts a current from the output terminal according to a level-shifting signal generated by level-shifting the second differential signal.

Abstract: A semiconductor device outputs, as an output signal synchronized to a phase-locked loop clock signal, a synchronized input signal that is synchronized to a reference clock signal of a phase-locked loop circuit. The semiconductor device includes the phase-locked loop circuit, a first flip-flop that receives the input signal in synchronization with the reference clock signal on the basis of a feedback signal inputted to a phase comparator of the phase-locked loop circuit 10, and a second flip-flop that receives an output from the first flip-flop on the basis of the phase-locked loop clock signal. The second flip-flop outputs the output from the first flip-flop as the output signal. A setup time to synchronize the input signal to the phase-locked loop clock signal is set to one half of a period of the reference clock signal.

Abstract: The semiconductor device and the method of fabricating the same includes, on a surface of a semiconductor substrate 1 of a first conductivity type which is P-type or N-type, a diode element using a PN junction including a high-concentration first conductivity type impurity region 6 of the first conductivity type, a high-concentration second conductivity type impurity region 5 of a second conductivity type that is a conductivity type opposite to the first conductivity type, and an element isolation region 2 sandwiched between the high-concentration first conductivity type impurity region and the high-concentration second conductivity type impurity region, and a floating layer 3 of the second conductivity type separated from the high-concentration second conductivity type impurity region below the high-concentration second conductivity type impurity region on the semiconductor substrate.

Abstract: A power reception device has: a rectifier circuit that generates a direct current voltage by having applied thereto an alternating current voltage, and has first and second output terminals that output the direct current voltage; a transistor, the drain and source of which are connected to the first and second output terminals; a gate driver circuit that controls the gate voltage of the transistor according to the voltage between the first and second output terminals; and a capacitor that has a first end that is connected to the drain of the transistor and a second end that is connected to the gate of the transistor.

Abstract: A playback device includes a playback function unit, a data signal monitoring unit configured to output a data change trigger signal based on a change in the data signal, a clock signal monitoring unit configured to output a clock change trigger signal based on a change in the clock signal, an enable signal monitoring unit configured to output an enabled/disabled state signal that indicates a disabled or enabled state of the enable signal, and a determining unit configured to determine whether the data signal, the clock signal, or the enable signal is properly inputted into the playback function unit or not, based on the data change trigger signal, the clock change trigger signal, and the enabled/disabled state signal.

Abstract: A foundation portion and a conductive base portion disposed on the foundation portion are formed on a temporary support, a semiconductor element electrically connected to the base portion is disposed on a side of the temporary support on which the foundation portion and the base portion are formed, and an insulating layer coming into a state of burying the foundation portion, the base portion, and the semiconductor element is formed on the temporary support. Subsequently, surfaces of the foundation portion and the insulating layer on a side of the temporary support are exposed by removing the temporary support, and the exposed foundation portion is further removed, thereby disposing the base portion in a state of being more recessed than the surface of the insulating layer. An external connection terminal is formed on the exposed base portion to manufacture the semiconductor package.

Abstract: A logic circuit includes an inverter that outputs from an output terminal a signal created by inverting the logic of a signal input into an input terminal, a first transistor that is connected to the input terminal in such a way as to maintain an OFF state, and a second transistor that is connected to the output terminal in such a way as to maintain an OFF state.

Abstract: In writing and reading data at a semiconductor storage device, control is carried out such that, at a time of a burst mode, in a case in which a value of a block address which is, from addresses assigned to a region of an internal address, an address for selecting a sense amplifier block from plural sense amplifier blocks, is a largest value, a first sense amplifier block and a second sense amplifier block are made to access different banks, and, in case in which the value of the block address is not the largest value, the first sense amplifier block and the second sense amplifier block are made to access a same bank of plural banks.

Abstract: A passive radio frequency identification (RFID) tag includes: a rectifier circuit that rectifies a signal obtained from an antenna and outputs the rectified signal as a DC voltage. A capacitor is connected to an output line of the rectifier circuit. A first regulator circuit generates a first regulator voltage by stabilizing the output DC voltage from the rectifier circuit. A control circuit starts operating when the first regulator voltage is applied, and the control circuit generates a control signal upon receipt of the modulation signal section of the wireless signal. A second regulator circuit generates a second regulator voltage by stabilizing the output DC voltage from the rectifier circuit in response to the control signal and outputs the second regulator voltage to the outside.

Abstract: A semiconductor device includes a circuit-to-be-adjusted in which an output characteristic thereof can be adjusted by a fuse that is controlled based on a fuse signal. The semiconductor device includes a control circuit using, as a power source, an internal power source that has a converted voltage obtained by converting a voltage of an external power source, the control circuit being configured to generate control signals A, B based on an inputted test signal, the control signals being able to adjust the circuit-to-be-adjusted in place of the fuse signal. The semiconductor device includes a selector circuit that selects the fuse signal before the internal power source reaches a stable state after the external power source is turned on, and selects the control signal CS after the internal power source has reached a stable state.

Abstract: A wireless communication apparatus which comprises: a shared antenna shared for communication and power reception; an impedance matching circuit connected to the shared antenna and having a first switch element; a communication circuit connected to the impedance matching circuit; a second switch element connected to the first switch element; and an impedance matching adjustment circuit configured to switch an on/off state of each of the first switch element and the second switch element at the time of communication and at the time of power reception.

Abstract: A power supply circuit in which an increase in a leakage current can be suppressed is provided. In a power supply circuit in which a main LDO unit outputs a first internal voltage during a normal operation and a sub LDO unit outputs a sleep voltage during a sleep operation, the sleep voltage is applied to a drain of a transistor, and an external voltage higher than the sleep voltage is applied to a gate and a back gate thereof.

Abstract: A semiconductor device including a FIFO circuit in which a data capacity can be increased while minimizing an increase in a circuit scale is provided. The semiconductor device includes a single-port type storage unit (11) which stores data, a flip-flop (12) which temporarily stores write data (FIFO input) or read data (FIFO output) of the storage unit (11), and a control unit (14, 40) which controls a write timing of a data signal, which is stored in the flip-flop (12), to the storage unit (11) or a read timing of the data signal from the storage unit to avoid an overlap between a write operation and a read operation in the storage unit (11).

Abstract: A semiconductor device includes a semiconductor chip including a communication circuit, a first antenna element formed in a first rewiring layer covering a first surface of the semiconductor chip and connected to the communication circuit, and a second antenna element formed in a second rewiring layer covering a second surface on the side opposite to the first surface of the semiconductor chip and connected to the communication circuit.

Abstract: The present invention includes: a first decoder that outputs mutually different two voltages as first and second selection voltages based on a first bit group of a digital data signal in a first selection state, and outputs one or both of the two voltages as the first and the second selection voltages in a second selection state; a second decoder that outputs mutually different two voltages as third and fourth selection voltages based on a second bit group of the digital data signal in the first selection state and outputs one voltage based on the second bit group as the third and the fourth selection voltages in the second selection state; and an amplifier circuit that averages a combination of the first and the second selection voltages or the third and the fourth selection voltages with predetermined weighting ratios and outputs the averaged voltage.

Abstract: A digital-to-analog conversion circuit includes: a decoder that, if set to a first selection state, selects two different reference voltages from a reference voltage group on the basis of a digital data signal and outputs the two reference voltages as first and second selection voltages, and if set to a second selection state, selects two reference voltages from the reference voltage group in a manner allowing redundancy and outputs the two reference voltages as the first and second selection voltages; and an amplifier circuit that amplifies and outputs a voltage obtained by averaging a combination of the first and second selection voltages with weighting factors set in advance.