Abstract: A digital-analog converter (DAC) comprises a receiving circuit configured to receive an input bit stream and generate a first bit signal stream of the input bit stream, a first delay circuit coupled to the receiving circuit to receive the first bit signal stream and to generate a second bit signal stream representing a delayed version of the first bit signal stream. The DAC also comprises a first current generation circuit to receive the first bit signal stream, the first current generation circuit configured to provide first current, corresponding to the first bit signal stream, to a first output. The DAC further comprises a second current generation circuit to receive the second bit signal stream and to provide second current to the first output responsive to receiving the second bit signal stream, a waveform of the second current inverted and scaled relative to a waveform of the first current.

Abstract: Embodiments of the invention are generally directed to a configurable single-ended driver. An embodiment of an apparatus includes an interface with a channel; and a single-ended driver to drive a signal on the channel, wherein the driver includes a mechanism to configure a termination resistance of the driver, configure a voltage swing of the driver, and configure a signal response of the driver.

Abstract: System, method, and apparatus for smoothing of edges in images to remove irregularities are disclosed. In one aspect of the present disclosure, a method of image processing includes, identifying an edge in an image having an associated set of edge characteristics, determining the associated set of edge characteristics, and applying a low pass filter to a pixel of the edge based on the associated set of edge characteristics to generate a second image based on the image, wherein the edge in the image is smoothed in the second image. The method further includes generating a third image which is a blend of the original image and the second (edge-smoothed) image based on the associated set of edge characteristics.

Abstract: The disclosed embodiments relate to a retro-directive array that facilitates a tracking operation. This retro-directive array includes a first antenna configured to receive an input signal which is substantially circularly polarized from a tracking device. The first antenna separates the input signal into two signal components (e.g., Ex and Ey) associated with different orthogonal polarizations, wherein the two signal components comprise a quadrature signal wherein Ey=j·Ex. The retro-directive array also includes a bi-directional quadrature gain (BQG) module coupled to the first antenna which is configured to boost the quadrature signal. It additionally includes a second antenna which configured to transmit the boosted quadrature signal to the tracking device.

Abstract: Embodiments of disclosed configurations include a circuit and system for a sense amplifier having a sensing circuit changing an output voltage at an output node based on a time that is defined by the output voltage reaching a threshold voltage level. The sensing circuit changes the output voltage at the output node before the time. In addition, a regeneration circuit amplifies the changed output voltage at the time. The sense amplifier offers sufficient voltage headroom to improve operation speed and power efficiency.

Abstract: An electronic device for wirelessly tracking the position of a second electronic device is disclosed. The electronic device includes transceiver circuitry and processing circuitry. The transceiver circuitry includes a beacon generator to generate a beacon at a particular frequency and direction. An antenna array transmits the beacon, and receives at least one modulated reflected beacon from the second electronic device. The transceiver circuitry also includes a discriminator to discriminate between received modulated reflected beacons and received reflected interfering beacons. The processing circuitry couples to the transceiver circuitry and tracks the position of the second device based on the modulated reflected beacons.

Abstract: The disclosed embodiments relate to a technique for calibrating a retro-directive array. During the calibration process, the system measures a gain g1 through a first pair of antennas in the retro-directive array. Next, the system measures a gain g2 through a second pair of antennas in the retro-directive array. The system then simultaneously measures a combined gain G1,2 through the first and second pairs of antennas in the retro-directive array. If G1,2 is less than g1+g2 by more than a threshold value, the system calibrates a phase relationship between the first and second pairs of antennas.

Abstract: A programmable logic device (PLD) is provided with a two-level voltage regulator for powering SRAM cells within the device. In one example, a PLD includes a plurality of static random access memory (SRAM) cells configured to store a configuration for the programmable logic device. The PLD also includes a two-level voltage regulator configured to selectively charge a first power supply node to a reduced voltage and to an enhanced voltage that is greater than the reduced voltage. The SRAM cells are powered through a coupling to the first power supply node. The PLD also includes a control circuit configured to control the two-level voltage regulator to charge the first power supply node to the reduced voltage during a write operation for the SRAM cells and to charge the first power supply node to the enhanced voltage during normal operation of the configured programmable logic device.

Abstract: A system that facilitates antenna selection and pilot reduction in a multi-antenna system is provided. During operation, in response to an activating event, the system performs a full pilot transmission by transmitting pilot signals through all available transmit antennas at a base station. The system then determines the selected subset of transmit antennas by receiving lists of selected antennas from mobile stations associated with preferred users, wherein a given mobile station selects a list of antennas in response to pilot signals received during the full pilot transmission. The system then combines the received lists to produce the selected subset, wherein the selected subset includes all antennas which appear in the received lists of selected antennas. Next, during normal system operation, the system periodically performs a selected pilot transmission by transmitting pilot signals through a selected subset of the available transmit antennas.

Abstract: A cable with circuitry that enables the cable to communicate data in one of at least two different signal modes of operation is presented. In a first signal mode, the cable enables data communication between the circuitry and either a source device or a sink device. The first signal mode can be used either to communicate properties of the cable itself or of a signal passing through the cable to either the source device or the sink device. In a second signal mode, the cable enables data communication between the source device and the sink device. The second signal mode can be used to communicate data in accordance with a predetermined protocol.

Abstract: A method for calibrating signal swing and a trip reference voltage. The signal swing of a system can be calibrated in a symmetric or asymmetric technique through adjustment of a drive parameter such as a supply voltage for a transmitter or a drive termination. The trip reference voltage of the system can also be calibrated in a symmetric or asymmetric technique through sampling of a data pattern to determine an ideal level of the trip reference voltage.

Abstract: Techniques and mechanisms for formatting digital audio-video (“AV”) information. In an embodiment, interface logic includes circuitry to receive digital AV information which, in one or more respects, is according to or otherwise compatible with a first interface specification. The interface logic changes a format of the digital AV information to allow for subsequent physical layer processing which is according to a second interface specification. In another embodiment, conversion logic receives analog signals according to the second interface specification and, based on such analog signals, performs digital information processing for subsequent generation of other analog signals to be transmitted according to the first interface specification.

Abstract: A device for communications over a multimedia communication interface. The device can be a source device including a scrambling circuit that receives control data associated with multimedia data to be transmitted over the multimedia channel of the multimedia communication interface, and generates scrambled control codes based on the control data. An encoding circuit generates transition minimized control codes based on the scrambled control codes. The device transmits the transition minimized control codes to a sink device via the multimedia channel. The sink device may also decode and de-scramble the transition minimized control codes received from the source device via the multimedia channel.

Abstract: A control circuit is provided that enables a register to provide a synchronous initialization capability as well as an asynchronous capability despite the register having no asynchronous input.

Abstract: Embodiments of a communication circuit are described. This communication circuit includes an input node to receive a set of data symbols and a partitioner coupled to the input node. This partitioner is to divide the set of data symbols into M irregular subgroups of data symbols, a given one of which includes non-consecutive data symbols in the set of data symbols. Moreover, this given irregular subgroup of data symbols includes at least two pairs of adjacent data symbols having different inter-data-symbol spacings in the set of data symbols. This communication circuit also includes M modulators coupled to the partitioner, where the given irregular subgroup of data symbols is coupled to a given modulator in the M modulators. Furthermore, the communication circuit includes M output nodes, where a given output node in the M output nodes is coupled to the given modulator and is to couple to an antenna element in M antenna elements.

Abstract: Embodiments of the invention describe a multimedia stream switch capable of multiplexing the audio and the video data of a multimedia stream separately. The multiplexing features of embodiments of the invention enable a multimedia stream switch to control each multimedia data type separately instead of multiplexing the whole streams (i.e., multiplexing sets of audio/video data together). Furthermore, prior art multimedia stream switches need to regenerate audio clocks by using phase locked loop (PLL) circuitry which incurs manufacturing and development costs. Embodiments of the invention provide the mixing of audio and video data from different sources without the need for PLL circuitry.

Abstract: Embodiments of the invention are generally directed to a single-ended configurable multi-mode driver. An embodiment of an apparatus includes an input to receive an input signal, an output to transmit a driven signal generated from the input signal on a communication channel, a mechanism for independently configuring a termination resistance of the driver apparatus, and a mechanism for independently configuring a voltage swing of the driven signal without modifying a supply voltage for the apparatus.

Abstract: Techniques and methods for performing asymmetric, full-duplex communication via a signal line. In an embodiment, a transceiver includes transmit circuitry to transmit a first signal via a node coupled to a signal line, where the first signal is transmitted concurrently with the transceiver receiving a second signal via the node at a substantially different data rate than that of the first signal. In another embodiment, signal processing circuitry of the transceiver detects a composite signal at the node, the composite signal including a combination of the first signal and the second signal. Based on the combination of the first signal and the second signal, the signal processing circuitry generates a processed signal, including the signal processing circuitry reducing a contribution by the first signal. The processed signal is provided to receiver circuitry of the transceiver.

Abstract: Embodiments of the invention are generally directed to determination of physical connectivity status of devices based on electrical measurement. An embodiment of a method includes discovering a connection of a first device with a second device, and performing an electrical measurement of the second device by the first device via the connection between the first device and the second device, where performing the electrical measurement includes sensing by the first device of an element of the second device. The method further includes, if the sensing by the first device fails to detect the element of the second device and a predetermined condition for the electrical measurement is enabled, then determining by the first device that the connection with the second device has been lost.

Abstract: In one embodiment, an integrated programmable device has a plurality of current sense amplifiers for reading data from non-volatile memory and a reference generator that provides common bias reference voltages to the sense amplifiers. The sense amplifiers can read data from the non-volatile memory at low power supply voltage levels (e.g., 750 mV) relative to the nominal supply level (e.g., 1.2V). Each sense amplifier has a trans-impedance amplifier that converts a memory bit-line current into a voltage level indicative of whether a selected memory cell is programmed or erased. The trans-impedance amplifier has a current mirror with a high-threshold regeneration device that lowers the sense amplifier's range of operating voltages. Each sense amplifier also has a level-shifted inverter that further lowers the sense amplifier's operating voltage range.