Abstract: The discovery of a topology of a network with an unknown topology can enable the selection of a data path within the network, and the establishment of a data stream over the selected data path. Routing tables mapping originating nodes to input ports can be created based on the receipt of discovery messages generated by the originating nodes. A source node can select a data path between the source node and a sink node in order to establish a data stream using the routing tables. Data paths can be selected based on, for instance, routing table bandwidth information, latency information, and/or distance information. Data streams can be established over the selected data path, and each node can release any reserved output bandwidth determined to be unnecessary for the data stream.

Abstract: A system for delivering power over a network of devices connected through a serial link includes a first and second differential pairs of wires. Each differential pair of wires is double AC coupled by a HPF on one side and by another HPF on an opposite side. An LPF connects a portion of each differential pair of wires between the HPFs to a voltage source, and another LPF connects that portion of each differential pair to a load. The system further includes a third and fourth differential pairs of wires. All four differential pairs of wires are located within a single cable, such as a CAT6 cable. The first, second and third differential pair of wires are used for video links, and the fourth differential pair of wires are used for the bi-directional hybrid link. A power delivery circuit in each device includes a voltage source, a power relay switch, a signature resistor for detection, and a load detector.

Abstract: Embodiments of the present disclosure relate to methods and device for receiving PAM data stream. In an embodiment, a method comprises receiving a signal stream modulated with pulse amplitude modulation (PAM) associated with a plurality of bit patterns; determining boundary voltages for the plurality of bit patterns; and calibrating, based on the boundary voltages, a threshold voltage for use in recognition of the plurality of bit patterns. In this way, bit patterns may be accurately recognized based on the calibrated threshold voltage.

Abstract: Techniques are provided to assign a set/reset signal of a user design to global set/reset (GSR) resources of a programmable logic device (PLD). By assigning a set/reset signal of the user design to the GSR resources during synthesis and prior to mapping, configurable resources consumed by the design may be reduced. In one example, a method includes receiving a user design for a programmable logic device (PLD) that comprises a plurality of configurable resources and global set/reset (GSR) resources. The method also includes identifying a plurality of set/reset signals of the user design. The method also includes determining, for each set/reset signal, a measurement of configurable resource savings associated with an assignment of the set/reset signal to the GSR resources. The method also includes assigning a selected one of the set/reset signals to the GSR resources based on the associated measurement. Additional methods and related systems are also provided.

Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes determining clock resources in a design identifying operations to be performed by a PLD, determining available clock resources of the PLD, determining a flow network model corresponding to the design and the PLD, and determining a clock resource placement based on the flow network model. The flow network model may include a plurality of levels of vertices disposed between source and sink vertices, where vertices are coupled to each other using edges with unit capacity.

Abstract: A method that calibrates a device for echo cancellation and a device with calibration for echo cancellation are provided. Devices may be calibrated such that the echo residual error is less than a threshold determined by the calibration accuracy. Non-ideal factors such as mismatch may be eliminated during calibration.

Abstract: One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.

Abstract: Embodiments relate to a voltage oscillator (VCO) that uses a replica bias circuit to generate a cascode bias voltage. The VCO generate an output periodic signal having a frequency and phase that is less or not susceptible to voltage swings by using a bias voltage generated in a replica bias circuit that replicates a voltage-to-current converter in the VOC. The bias voltage is generated and regulated according to a power supply voltage that supplies power to the VCO to account for voltage variations in the power supply voltage.

Abstract: Embodiments relate to identifying a topology of a network based on information identifying adjacent devices from each of the devices in the network. In one embodiment, each device identifies one or more adjacent devices within one hop and stores information identifying the one or more adjacent devices. A requesting device aggregates information identifying one or more adjacent devices of each device and identifies the topology of the network based on the aggregated information. By each device storing and transmitting information identifying adjacent devices connected within one hop, amount of information stored in each device and bandwidth of information exchanged can be reduced.

Abstract: Embodiments of the invention are generally directed to partial encryption of data stream. An embodiment of a method includes receiving, at a data transmitting device, a data stream having content including one or more of audio content, video content, and control content, determining one or more content that are to be encrypted. The method further includes partially encrypting the data stream by encrypting the one or more content, and leaving other content unencrypted, and transmitting, from the data transmitting device, the partially encrypted data stream to a data receiving device.

Abstract: In one aspect, a video processing device includes a processor and a transmitter, for example implemented as separate integrated circuits on a printed circuit board. Pins on the processor are coupled to pins on the transmitter via a data channel, for example conductive leads on the printed circuit board. Video data is transmitted from the processor to the transmitter via this data channel, which is high speed enough to accommodate video data. The transmitter also includes an encryption engine used to encrypt the video data. Encryption control data, which determines the encryption to be applied, is transmitted from the processor to the transmitter over the same data channel as the video data. This is more secure than transmitting the encryption control data over a slower separate data channel, because the high speed video channel is harder to tamper with.

Abstract: A method for transcoding data comprises receiving an input stream of data formatted according to a USB standard, the input stream is partitioned into a sequence of blocks having a fixed length. At least one input block of the input stream comprises one or more data symbols and one or more control symbols, the one or more control symbols include one or more general control symbols. The method also includes transcoding the at least one input block to generate at least one output block comprising a synchronization block and a control/data block. The control/data block comprises the one or more data symbols of the at least one input block, a representation of the one or more general control symbols of the at least one input block, and a plurality of indicators indicating locations of the one or more data symbols and control symbols in the at least one input block.

Abstract: In certain embodiments, an integrated circuit has scan-test circuitry that performs scan testing on circuitry under scan test (CUST) within the IC, where the scan-test circuitry is susceptible to a defect. In order to enable the defect to be corrected after it occurs, the scan-test circuitry includes a set of programmable circuitry connected to provide a signal to other circuitry (e.g., a scan chain) within the scan-test circuitry, where the set of programmable circuitry includes one or more configurable memory cells connected to control the programming of the set of programmable circuitry. The memory cell(s) can be configured to program the set of programmable circuitry to enable the scan testing to be performed without modification. The memory cell(s) can also be configured to program the set of programmable circuitry to modify the scan testing to correct the defect in the scan-test circuitry.

Abstract: Using relatively inexpensive, external resistor networks, an electronic device, such as an FPGA, can be configured to use non-MIPI interfaces to communicate with one or more MIPI-compliant devices, such as video sources (e.g., cameras) and sinks (e.g., displays). High-speed (HS) and low-power (LP) MIPI signaling for each MIPI clock/data lane is supported by a set of one or more non-MIPI interfaces, such as LVDS and/or LVCMOS receivers, transmitters, and/or transceivers, and an appropriate, corresponding, external resistor network. For configurations in which the resistor-configured electronic device can handle high-speed MIPI data from a MIPI-compliant device, the electronic device can detect transitions in the MIPI mode of the MIPI-compliant device. In some configurations, the resistor-configured electronic device can provide high-speed MIPI data to a MIPI-compliant device. In either case, the electronic device configures the non-MIPI interfaces to support the current MIPI HS/LP mode.

Abstract: An electronic device for wirelessly tracking the position of a second electronic device is disclosed. The electronic device includes transceiver circuitry having a beacon generator to generate a beacon at a particular frequency and direction. An antenna array transmits the beacon, and receives at least one reflected beacon from the second electronic device. The reflected beacon is received if a position of the second electronic device lies within a range of directions of the beacon. The transceiver circuitry further includes an injection-locked oscillator having an input coupled to the antenna array to receive reflected beacons, and to lock to the reflected beacon when the reflected beacon has a frequency value within locking range of the oscillator. Processing circuitry coupled to the transceiver circuitry tracks the position of the second device based on the lock condition of the oscillator.

Abstract: Embodiments of the invention are generally directed to transmission and detection of multi-channel signals in reduced channel format. An embodiment of a method for transmitting data includes determining whether a first type or a second type of content data is to be transmitted, where the first type of content data is to be transmitted at a first multiple of a base frequency and the second type of data is to be transmitted at a second multiple of the base frequency. The method further includes selecting one or more channels from a plurality of channels based on the type of content data, clocking a frequency on the first or second multiple of the base frequency according to the type of content data in the selected channels, modifying the content data to fit within a single output channel, and transmitting the modified data via a single output channel at the chosen multiple of the base frequency.

Abstract: Embodiments of the invention are generally directed to communication bridging between devices via multiple bridge elements. An embodiment of an apparatus includes a transmitter element to transmit data, and multiple bridge elements, the bridge elements including a first bridge element to receive data from the transmitter element and a second bridge element to provide data to a receiver. The bridge elements provide for one or more of translation of one or more commands for an operation from the transmitter element, wherein translation of commands includes handling of a command intended for the receiver, and pre-fetching of one or more data for the operation from the receiver.

Abstract: The discovery of a topology of a network with an unknown topology can enable the selection of a data path within the network, and the establishment of a data stream over the selected data path. Routing tables mapping originating nodes to input ports can be created based on the receipt of discovery messages generated by the originating nodes. A source node can select a data path between the source node and a sink node in order to establish a data stream using the routing tables. Data paths can be selected based on, for instance, routing table bandwidth information, latency information, and/or distance information. Data streams can be established over the selected data path, and each node can release any reserved output bandwidth determined to be unnecessary for the data stream.

Abstract: The discovery of a topology of a network with an unknown topology can enable the selection of a data path within the network, and the establishment of a data stream over the selected data path. Routing tables mapping originating nodes to input ports can be created based on the receipt of discovery messages generated by the originating nodes. A source node can select a data path between the source node and a sink node in order to establish a data stream using the routing tables. Data paths can be selected based on, for instance, routing table bandwidth information, latency information, and/or distance information. Data streams can be established over the selected data path, and each node can release any reserved output bandwidth determined to be unnecessary for the data stream.

Abstract: Various techniques are provided to implement user specified test registers locally on a PLD for use while the PLD is configured with a user design and tested. In one example, a machine-implemented method includes receiving, from an external test application, a data value at a programmable logic device (PLD) running configured user logic. The method also includes writing the data value into a test register of the PLD. The method also includes providing a control signal from the test register to the configured user logic in response to the data value. The method also includes switching operation of the configured user logic from a first test implementation to a second test implementation in response to the control signal.