Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a mixed-mode memory operation in the design. The mixed-mode memory operation specifies memory access having different read and write data widths using a plurality of embedded memory blocks each having a fixed data width. The synthesizing further includes determining a reduced number of embedded memory blocks to implement the mixed-mode memory operation, and modifying the mixed-mode memory operation to remap the memory access to the reduced number of embedded memory blocks.

Abstract: Embodiments relate to type-I PLLs that do not lock at a sub-harmonic frequency of a reference clock signal by controlling timing of charging or discharging of one or more capacitors in the PLLs. A phase frequency detector (PFD) of a type-I PLL can prevent sub-harmonic locking by generating a clear output signal to cause a sampling capacitor of PLL's loop filter to discharge only during a time period when the sampling capacitor is not being charged. For example, the PFD can include a gating element to control the time during which the clear output signal is generated. By ensuring that the sampling capacitor is not discharged during a time period while it is being charged, the PLL's voltage-controlled oscillator is controlled to oscillate at an intended frequency rather than at a sub-harmonic of the intended frequency.

Abstract: In one embodiment, the operating range of an over-current detection circuit is extended to higher input voltage levels by providing a reference-voltage generation circuit for the detection circuit with voltage protection circuitry that applies an additional voltage drop to shield other vulnerable transistor devices from the higher input voltages. In addition, bypass circuitry is provided that is inactive at the highest input voltage levels, but actively bypasses at least some of the voltage protection circuitry at relatively low input voltage levels to apply a voltage drop that is sufficient to ensure proper operation of the vulnerable transistor devices at the low voltage levels. In one implementation, the vulnerable transistor devices are NFET devices in a programmable current mirror of the reference-voltage generation circuit. In addition, a stiffened voltage divider helps to ensure sufficient voltage drop at the low voltage levels. The protection and bypass circuitry also enable hot-socketing operations.

Abstract: Embodiments related to storing and utilizing information of a sink device for establishing communication. A source device retrieves the information of a previously connected sink device stored in the source device to reduce data exchanged during a handshaking operation. Information of the sink device not stored in the source device may be stored in the source device for future usage. The source device receives identification information of the sink device via a medium. The source device also searches for capabilities information associated with the identification information in the source device. In addition, the source device encodes the content for transmission to the sink device via the medium in a format compliant with capabilities of the sink device according to the capabilities information.

Abstract: A device converts between electrical duplex and optical signals. In one embodiment, such a device includes an echo cancellation circuit that reduces the echo from an incoming optical signal.

Abstract: A transmitter and receiver for communication of multimedia streams across a multi-lane communications link. The transmitter packetizes multimedia streams according to a link layer protocol and distributes the packets across multiple lanes of a communications link. The entire packet, including the header and payload, can be distributed across the lanes in an ordered sequence to increase utilization of the communication lanes. The transmitter may also packetize multiple multimedia streams and intermix the packets across the lanes of the communication lane. The receiver extracts the packets that are distributed across the multiple lanes and decodes the packets into the multimedia streams.

Abstract: A programmable logic is provided that uses only NMOS pass transistors to pass a true output signal to an internal true node and to pass a complement output signal to an internal complement node. The internal true and complement nodes are cross-coupled through PMOS transistors so that the discharge of one of the internal true and complement nodes switches on a corresponding one of the cross-coupled PMOS transistors to charge a remaining one of the internal true and complement nodes.

Abstract: In one memory array embodiment, in order to compensate for bit-line leakage currents by OFF-state bit-cell access devices, a leakage-current reference circuit tracks access-device leakage current over different process, voltage, and temperature (PVT) conditions to generate a leakage-current reference voltage that drives a different leakage-current abatement device connected to each different bit-line to inject currents into the bit-lines to compensate for the corresponding leakage currents. In one implementation, the leakage-current reference circuit has a device that mimics the leakage of each access device configured in a current mirror that drives the resulting leakage-current reference voltage to the different leakage-current abatement devices.

Abstract: Systems and methods are provided for generating accurate current ratios from a current mirror including an array of output transistor and a corresponding array of switches. Each switch couples in series with its corresponding output transistor. A control logic circuit controls the switches to cancel mismatches for the output transistors.

Abstract: In one embodiment, an integrated circuit includes multiple I/O banks, each bank having multiple I/O-ESD tiles, each tile having one or more I/O circuits and electrostatic discharge (ESD) protection circuitry for the one or more I/O circuits in the tile. The ESD circuitry for one tile includes at least one RC-triggered clamp, whose resistance is provided by a resistor shared by one or more other RC-triggered clamps in one or more other tiles of the same bank and whose capacitance is provided by a combination of distributed capacitors, one for each of those two or more RC-triggered clamps. Each tile may have multiple instances of such RC-triggered clamps providing ESD protection for different (e.g., power supply and/or bus) nodes. The shared resistors are variable to allow different instances of the same ESD circuitry design to be implemented with the same time constant for different banks having different numbers of tiles.

Abstract: A multimedia system for data communications. A source device communicates data over a full duplex control channel of a multimedia communication link. The source device has a first link layer that retries unsuccessful data communications over the full duplex control channel until a first maximum retry limit of the first link layer is reached. A sink device communicates data over the full duplex control channel of the multimedia communication link. The sink device has a second link layer that retries unsuccessful data communications over the full duplex control channel until a second maximum retry limit of the second link layer is reached, where the second maximum retry limit is different than the first maximum retry limit.

Abstract: Transmitting a bidirectional, virtual differential signal in addition to other differential signals over physical communication channels. Thus, four signal lines can provide three differential signals, where the virtual differential signal is bidirectional. The virtual differential signal can be provided over one or more of the other physical communication channels. Additional configurations allow for providing a bidirectional DC power supply. Additional configurations allow for providing DC power in addition to data over a reduced number of lines. Selective switching of signal lines can allow backward and forward interoperability with other standard interfaces.

Abstract: The disclosed embodiments relate to a system that performs channel-sounding operations in a multi-antenna wireless communication system. During operation, the system first performs channel-sounding operations between a first client and a second client in a first frequency band. These channel-sounding operations involve transmitting a series of known tones between the first client and the second client and using signals received as a result of the transmissions to finds a strongest path between the first client and the second client. Next, the system uses the identified strongest path to improve channel-sounding operations in a second frequency band.

Abstract: In one embodiment, a memory array has a pair of bit lines for each column of 1-bit SRAM cells and a word line for each row of cells, where, during a memory read operation, the bit value stored in each cell is detectable by sensing a voltage difference developed between the corresponding bit line pair. A first signal-development circuit is coupled to one bit line to accelerate draining that bit line of charge if a first bit value is stored in the cell, and a second signal-development circuit is coupled to the other bit line to accelerate draining that other bit line of charge if a second, different bit value is stored in the cell. Pulldown devices are provided to ensure that the signal-development circuit operate properly during the pre-charge and voltage difference development phases of the memory read operation, which is now faster due to the signal-development circuits.

Abstract: A method for calibrating signal swing and a trip reference voltage. The signal swing of a system can be calibrated in a symmetric or asymmetric technique through adjustment of a drive parameter such as a supply voltage for a transmitter or a drive termination. The trip reference voltage of the system can also be calibrated in a symmetric or asymmetric technique through sampling of a data pattern to determine an ideal level of the trip reference voltage.

Abstract: Embodiments of the invention are generally directed to a multimedia I/O system architecture for advanced digital television. An embodiment of a multimedia system includes an I/O (input/output) control chip, the I/O control chip including one or more audio/video sub-processing engines for the processing of one or more data streams; a processing core chip for the processing of data, including audio/video data received from the I/O control chip; and one or more shared I/O channels for the transfer of data between the I/O control chip and the processing core chip.

Abstract: In one embodiment, an integrated circuit has hot-socket circuitry to protect I/O drivers during hot-socket events. The hot-socket circuitry has (i) N-well-to-pad switcher circuitry that ties driver PMOS N-wells to pads when the pad voltages are greater than the power-supply voltage and (ii) N-well-to-power-supply switcher circuitry that ties the driver PMOS N-wells to the power supply when the pad voltages are less than the power-supply voltage. The hot-socket circuitry also has a special PMOS device connected between the pad and a gate of at least one other PMOS device in the N-well-to-power-supply switcher circuitry to turn off the N-well-to-power-supply switcher circuitry quickly whenever the pad voltage is greater than the power-supply voltage. Applying a reduced power-supply voltage level to the gate of the special PMOS device enables the hot-socket circuitry to be implemented without having to use low Vt devices and without having to implement substantially large drive strengths.

Abstract: A mechanism for facilitating dynamic counter synchronization and packetization for data streams being communicated over communication devices is described. In one embodiment, a method includes detecting an audio/video (A/V) data stream being encrypted and/or decrypted using one or more high-bandwidth digital content protection (HDCP) engines, where the A/V data stream is communicated between a source device and a sink device. The method may further include dividing a video stream portion of the A/V data stream into a plurality of frames if the A/V data stream relates to a high-definition multimedia interface (HDMI), and synchronizing counter values with indicators within the plurality of frames.

Abstract: Embodiments relate to routing encrypted data from a source to a sink via a router without decrypting the data in the router. The source authenticates with the router, the result of which produces a session key and a pseudo-random number. The router authenticates with the sink using the same session key and pseudo-random number. The router passes encrypted data received from the source to the sink without decryption and re-encryption.

Abstract: A system of devices includes a plurality of devices such as a sink device, a source device and an intermediate device. In one embodiment, a first device propagates to a second device, via a multimedia link, an address of the first device in association with an indication that the first device is a master for a remote control command type. The second device responsive to receiving a remote control command from a remote control identifies the remote control command type of the remote control command. Responsive to the command type of the received remote control command being the remote control command type that the first device is the master for, the second device forwards the received remote control command using the address of the first device. The first device upon receiving the remote control command modifies a multimedia output by the first device based on the remote control command received.