Abstract: In one embodiment, an HDMI connector includes a plurality of conductive paths. The plurality of conductive paths correspond to four channels, i.e., three differential data channels and one differential clock channel. Each channel includes three conductive paths, which correspond to a differential pair and a dedicated ground. Each conductive path has a contact on one end and a pin on the opposite end. The pins of the plurality of conductive paths are arranged to attach to corresponding surface mounting pads in at least two columns of contact points. For each channel, the pad for the dedicated ground is larger than the pads for the differential pair, thereby providing shielding between the differential pairs of different channels.

Abstract: Exemplary embodiments of methods and apparatuses to provide an electro-optical alignment are described. An electrical connector is formed on a printed circuit board substrate that extends onto a side surface of the substrate to form an electrical turn. An optoelectronic die is placed onto the printed circuit board substrate. The optoelectronic die on the printed circuit board substrate is erected over a mounting board to provide optical coupling substantially parallel to the mounting board.

Abstract: Embodiments of the invention are generally directed to simultaneous transmission of clock and bidirectional data over a communication channel. An embodiment of a transmitting device includes a modulator to generate a modulated signal including a clock signal and a data signal, the clock signal being modulated by a first signal edge of the modulated signal and the data signal being modulated by a position of a second signal edge of the modulated signal; a driver to drive the modulated signal on a communication channel; an echo canceller to subtract reflected signals on the communication channel; and a data recovery module to recover a signal received on the communication channel, the received signal being encoded by Return-to-Zero (RZ) encoding, the signal being received simultaneously with driving the modulated signal on the communication channel.

Abstract: In one embodiment, a voltage-controlled oscillator has a ring of delay stages and power-regulating circuitry regulating power to each delay stage. Each delay stage has at least one inverter having a leg having a current regulator that controls current flowing through the leg and thereby controlling gain of the delay stage. The VCO receives three control signals that affect the amount of delay applied by each delay stage and therefore the VCO output frequency: a first applied to control the power-regulating circuitry, a second applied to at least one transistor gate in the current regulator, and a third applied to at least one transistor body in the current regulator. The power-regulating circuitry has a parallel configuration of a power-regulating transistor, a first capacitor, and a switched-capacitor leg having a second capacitor and a switch for controlling settling time. The capacitors regulate the power supply without a dedicated, opamp-based voltage regulator.

Abstract: A multimedia system for data communications. A source device communicates over a full duplex control channel of a multimedia communication link using time domain multiplexed (TDM) frames having n time slots per frame. The source device allocates a first time slot position to a virtual channel for data transmission by the source device over the full duplex control channel. A sink device communicates over the full duplex control channel of the multimedia communication link. The sink device allocates a second time slot position to the virtual channel for data transmission by the sink device over the full duplex control channel. A timing of the second time slot position is offset from a timing of the first time slot position by substantially n/2 time slots.

Abstract: Embodiments describe techniques for utilizing fractional-N phase locked loops (PLL). Some embodiments describe a fractional-divider based fractional-N PLL for a spread spectrum clock (SSC) generator that utilizes phase average techniques to suppress phase interpolator nonlinearity. Some embodiments describe a fractional-N PLL based on fractional dividers with hybrid finite impulse response (FIR) filtering. Some embodiments describe a small size and low power divider for a hybrid FIR fractional-N PLL.

Abstract: Embodiments relate to successive approximation register (SAR)-based analog-to-digital converters (ADCs) that increase a time frame allocated for the settling of capacitors in a digital-to-analog converter (DAC) capacitor network by feeding a comparator output signal to the DAC to begin DAC capacitor settling before the comparator output is latched by a clock signal at a latching time. The SAR ADC can include a window circuit that provides the comparator output directly from the comparator to the DAC before the latching time of the comparator. After the latching time, the latched version of the comparator output is provided to the DAC capacitor. By providing the capacitor output to the DAC capacitor before latching, DAC capacitor can settle earlier compared to an SAR ADC where DAC capacitor settling begins after the latching time of the comparator.

Abstract: Embodiments of the invention are generally directed to multiple protocol tunneling using time division operations. An embodiment of an apparatus includes an interface for communication with a second apparatus, the interface including a shared communication link; and a multiplexer to multiplex data of each of multiple protocols into time slots for transmission, the protocols including a first protocol. The time slots are distributed among the protocols, where the distribution of the time slots among the protocols includes assigning one or more time slots to the first protocol to enable the data of the first protocol to meet one or more performance requirements for the first protocol.

Abstract: Embodiments of the invention are generally directed to a linear regulator with improved power supply ripple rejection. An embodiment of an apparatus includes an linear regulator to receive a system power supply and to generate a regulated power supply; a first voltage reference generator to generate a first voltage reference for the linear regulator; a second voltage reference generator to generate a second voltage reference for the linear regulator; and a voltage reference and power switcher. In some embodiments, the voltage reference and power switcher is to switch a voltage reference for the linear regulator from the first voltage reference to the second voltage reference and is to switch a part of a power supply for the linear regulator from the system power supply to the regulated power supply.

Abstract: A cable with circuitry that enables the cable to communicate data in one of at least two different signal modes of operation is presented. In a first signal mode, the cable enables data communication between the circuitry and either a source device or a sink device. The first signal mode can be used either to communicate properties of the cable itself or of a signal passing through the cable to either the source device or the sink device. In a second signal mode, the cable enables data communication between the source device and the sink device. The second signal mode can be used to communicate data in accordance with a predetermined protocol.

Abstract: Embodiments relate to a receptacle assembly for connecting to a plug of a connector. The receptacle includes a first contact on a first side of an insulating member. The first contact electrically connects to a first plug contact when the connector engages with the receptacle in a first orientation. The receptacle includes a second contact on a second side of the insulating member. The second contact electrically connects to the first plug contact when the connector engages with the receptacle in a second orientation. The second contact extends to a printed circuit board and is connected to the first contact via a first conductive bridge at a first location closer to the printed circuit board than the first plug contact. The first and second contacts are connected via a second conductive bridge at a second location closer to the first plug contact than the first conductive bridge.

Abstract: Various techniques are provided to generate designs for programmable logic devices (PLDs). In one example, a computer-implemented method includes selectively grouping a first plurality of logic components for a first design into a plurality of partitions. The method also includes selectively merging at least a subset of the partitions of the first design. The method also includes converting each partition into a corresponding first physical implementation for a PLD. The method also includes comparing the first plurality of logic components to a second plurality of logic components for a second design to identify changed and unchanged partitions. The method also includes converting each changed partition into a corresponding second physical implementation for the PLD. The method also includes combining the first physical implementations for the unchanged partitions, with the second physical implementations for the changed partitions.

Abstract: Embodiments of the invention are generally directed to proxy device operation in a command and control network. An embodiment of a method includes discovering one or more devices in a first network at a proxy device, generating by the proxy device virtual devices representing the one or more devices, and advertising by the proxy device the one or more virtual devices on a second network. The method includes receiving by the proxy device a command for a first virtual device of the one or more virtual devices from a command device, the command device being outside the first network, the command being received via the second network, and the first virtual device representing a target device located in the first network. The method further includes forwarding the command to the target device via the first network.

Abstract: The defect-containing die identified from an inspection layer analysis subsequent to a manufacturing step for a wafer including a plurality of die and as well as the faulty die identified from a fault testing of the wafer are processed to identify a subset of the die that both contain a defect and are faulty. A probability analysis is performed to determine a confidence level of whether the die in the subset are faulty due to their defects.

Abstract: Embodiments relate to successive approximation register (SAR)-based analog-to-digital converters (ADCs) that increase a time frame allocated for the settling of capacitors in a digital-to-analog converter (DAC) capacitor network by feeding a comparator output signal to the DAC to begin DAC capacitor settling before the comparator output is latched by a clock signal at a latching time. The SAR ADC can include a window circuit that provides the comparator output directly from the comparator to the DAC before the latching time of the comparator. After the latching time, the latched version of the comparator output is provided to the DAC capacitor. By providing the capacitor output to the DAC capacitor before latching, DAC capacitor can settle earlier compared to an SAR ADC where DAC capacitor settling begins after the latching time of the comparator.

Abstract: A system for receiving and decrypting media content encrypted according to the HDCP protocol is described herein. A receiving device coupled to a plurality of content channels includes an authentication engine to authenticate each content channel and to generate an initial session key associated with each authenticated content channel. The content channels can be, for example, an HDMI channel or an MHL3 channel. A session key indicator indicating a session key used to encrypt media content is received, and an updated session key is generated. The receiving device also includes a stream cipher engine configured to decrypt received encrypted media content using the updated session key. Decrypted media content can then be displayed, for instance on a display of the receiving device.

Abstract: The disclosed embodiments generally relate to techniques for processing signals received from multiple antennas. More specifically, the disclosed embodiments relate to a system that uses an integrated phase-shifting-and-combining circuit to process signals received from multiple antenna elements. This circuit applies a specified phase shift to the input signals, and combines the phase-shifted input signals to produce an output signal. In some embodiments, the integrated phase-shifting-and-combining circuit uses a current-steering mechanism to perform the phase-shifting-and-combining operations. This current-steering mechanism operates by converting the input signals into associated currents, and then steering each of the associated currents through multiple pathways which have different delays. Next, the currents from the multiple pathways for the associated currents are combined to produce the output signal.

Abstract: Embodiments of the invention are generally directed to combining multiple video and audio streams utilizing pixel repetition bandwidth. An embodiment of an apparatus includes a buffer to receive pixel data and a clock of a first video data stream; and a multiplexer to remove pixel repetition of a second video data stream and combine the pixel data of the first and second video data streams to generate a merged data stream, the multiplexer to alternate between the pixel data of the first and second video data streams in the merged data stream. The merged data stream includes pixel data of the first and second video data streams in a line of data, the line of data including control information identifying the pixel data of the first and second video data streams.

Abstract: Embodiments of the invention are generally directed to conversion of multimedia data streams for use by connected devices. An embodiment of a method for processing data includes receiving a data stream in a first multimedia data format at a first device, and inserting a replacement video portion into the received data stream to generate a modified multimedia data stream in a second multimedia data format. The modified data stream is provided to a second device coupled to the first device.

Abstract: Embodiments of a circuit are described. In this circuit, a modulation circuit provides a first modulated electrical signal and a second modulated electrical signal, where a given modulated electrical signal, which can be either the first modulated electrical signal or the second modulated electrical signal, includes minimum-shift keying (MSK) modulated data. Moreover, a first phase-adjustment element, which is coupled to the modulation circuit, sets a relative phase between the first modulated electrical signal and the second modulated electrical signal based on a phase value of the first phase-adjustment element. Additionally, an output interface, which is coupled to the first phase-adjustment element, is coupled to one or more antenna elements which output signals. These signals include a quadrature phase-shift-keying (QPSK) signal corresponding to the first modulated electrical signal and the second modulated electrical signal.