Abstract: Embodiments of the invention are generally directed driving data of multiple protocols through a single set of pins. An embodiment of an apparatus includes a transmitter connected to two pads on an IC the transmitter including a differential driver to transmit a differential signal, wherein the differential driver has a first branch and a second branch, each branch of the differential driver including a protection device connected to one of the pads; and a common mode driver to transmit a common mode signal, the common mode driver having a first branch and a second branch, each of the branches of the common mode driver including a protection device connected to one of the pads. The first and second switch devices are not turned on simultaneously, based on data to be transmitted, one of the switch devices being turned on and the other being turned off.

Abstract: A Class AB amplifier has a control stage and a push-pull stage. The control stage has a programmable resistor that allows a floating constant voltage to applied to the push-pull stage such that the quiescent current of the amplifier is relatively low. The configuration enables the amplifier to operate properly at relatively low power-supply voltage levels. The amplifier can be configured as the output driver for an operational amplifier (op-amp) with a Miller compensation configuration that replaces the conventional Miller compensation resistor with a transistor that is part of the op-amp.

Abstract: Embodiments of the invention are generally directed to elements to counter transmitter circuit performance limitations. An embodiment of an apparatus for driving data on a differential channel including a first output terminal and a second output terminal includes a differential driver circuit; and a first pre-driver and a second pre-driver, where each pre-driver has an output, wherein the first output terminal of the apparatus is coupled to the output of the first pre-driver, and the second output terminal of the apparatus is coupled to the output of the second pre-driver, where each pre-driver includes one or more capacitors, a first end of each capacitor being connected to the output of the pre-driver and a second end of each of the capacitors being connected to a sub-pre-driver circuit.

Abstract: Techniques and mechanisms for switching between a plurality of inputs each to receive a respective analog signal to be transmitted. In an embodiment, switch circuitry comprises a first input to receive a first signal, a second input to receive a second signal, and one or more T-coil circuits including a first T-coil circuit. A first configuration of the switch circuitry includes a first signal path via a first switch coupled between the first input and a primary input node of the first T-coil circuit. A second configuration of the switch circuitry includes a second signal path via a second switch coupled between the second input and a secondary input node of the first T-coil circuit. In an embodiment, control logic transitions the switch circuitry among a plurality of configurations including the first configuration and the second configuration.

Abstract: A system may include a video link and a hybrid link that connects a transmitting device to the receiving device, and at least one intermediate hop between the transmitting device and the receiving device. The intermediate hop may be configured to relay video content from the video source to the video sink through the hybrid link using one or more data relay modes. The hybrid link may be configured to perform hybrid link control signaling (HLCS) to manage a physical layer of the hybrid link. The video link between the video source and the video sink may be configured to transmit a video stream the from video source to the video sink over one or more video lanes. A video link training may be implemented for the video link and the hybrid link.

Abstract: A place and route technique is provided for a programmable logic device to optimize a delay difference between a bus including a plurality of clock to out paths and a corresponding clock out path.

Abstract: A mechanism for facilitating dynamic phase detection with high jitter tolerance for images of media streams is described. In one embodiment, a method includes calculating stability optimization of an image of a media stream based on a plurality of pixels of two or more consecutive frames relating to a plurality of phases of the image, calculating sharpness optimization of the image, and selecting a best phase of the plurality of phases based on the stability and sharpness optimization of the image. The best phase may represent the image such that the image is displayed in a manner in accordance with human vision perceptions.

Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a programmable logic device (PLD). The computer-implemented method also includes synthesizing the design into a plurality of PLD components comprising a first logic block cascaded into a second logic block. In the computer-implemented method, the second logic block implements a multiplexer adapted to selectively pass a first multi-bit input signal received from the first logic block or a second multi-bit input signal. The computer-implemented method also includes further synthesizing the design to absorb the multiplexer into the first logic block.

Abstract: Embodiments of the invention are generally directed to compensation for common mode signal swing. An embodiment of an apparatus includes a connector for the transfer of the data, the connector including connections for a first set of one or more conductors; a receiver for the reception of data via the connector, the received data including a first signal and a second signal transmitted via the set of one or more conductors, the second signal being a common mode signal modulating the first signal, the receiver including an amplifier to amplify the received data with a positive gain; and a common mode compensation circuit to compensate for a voltage swing of the common mode signal in the amplified received data. The common mode compensation circuit is to sense the common mode signal, amplify the sensed common mode signal with a negative gain, and feed back the amplified common mode to output nodes of the receiver.

Abstract: A method and apparatus for interfacing integrated circuit chips is disclosed. In one embodiment, the interface includes a set of differential data lines over which a variable length register transaction can be conducted.

Abstract: Embodiments of the invention are generally directed to determination of physical connectivity status of devices based on electrical measurement. An embodiment of a method includes discovering a connection of a first device with a second device, and performing an electrical measurement of the second device by the first device via the connection between the first device and the second device, where performing the electrical measurement includes sensing by the first device of an element of the second device. The method further includes, if the sensing by the first device fails to detect the element of the second device and a predetermined condition for the electrical measurement is enabled, then determining by the first device that the connection with the second device has been lost.

Abstract: In one embodiment, a source device and sink device communicate with one another via a multimedia link. The multimedia link includes a cable and a plug. The cable includes one or more data lines, power lines, ground lines or control bus lines. The plug includes a plurality of pins each connected to the one or more lines included in the cable. The plug also includes a ground plane and a power plane, wherein a ground pin of the plug connects the ground plane to the ground line of the cable of the multimedia link and a power pin of the plug connects the ground plane to the power line of the cable. In one example, the ground plane and power plane are placed within a threshold distance of one another, such that the power line connected to the power plane via the power pin behaves as a signal return path.

Abstract: Embodiments of the invention are generally directed to a line driver with separate pre-driver for feed-through capacitance. An embodiment of an apparatus includes a differential pair of transistors to generate an output signal on a first output node and a second output node; a pass-through capacitance coupled with the first output node and the second output node; a first pre-driver to drive an input signal for the differential transistors; and a second pre-driver to drive the input signal for the pass-through capacitance.

Abstract: In one embodiment, a ball grid array (BGA) of a packaged semiconductor device and a corresponding landing pad array of a printed circuit board each have a layout defined by an interconnection array having (i) an inner sub-array of locations having connectors arranged in rows and columns separated by a specified pitch and (ii) an outer rectangular ring of locations having connectors arranged in rows and columns separated by the specified pitch. The outer rectangular ring is separated from the inner sub-array by a depopulated rectangular ring having a width of at least twice the specified pitch, wherein the depopulated rectangular ring has no connectors. The outer rectangular ring has empty locations having no connectors. Some of those empty locations define depopulated sets that divide the outer rectangular ring into a number of different contiguous sets of locations having connectors that enable pin escape for connectors of the device's BGA.

Abstract: Various techniques are provided to correct for hold time violations using input/output (I/O) block hardware of a programmable logic device (PLD) without requiring additional mapping, placement, or routing operations. In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The method also includes assigning components of the PLD to perform the operations. The method also includes routing a signal path among the components. The method also includes detecting a hold time violation for the signal path at an I/O block of the PLD. The method also includes selectively adjusting a variable delay cell of the I/O block to correct the hold time violation.

Abstract: Embodiments of the invention are generally directed to conversion of multimedia data streams for use by connected devices. An embodiment of a method for processing data includes receiving a data stream in a first multimedia data format at a first device, and inserting a replacement video portion into the received data stream to generate a modified multimedia data stream in a second multimedia data format. The modified data stream is provided to a second device coupled to the first device.

Abstract: In several embodiments of the invention, a programmable architecture for FIR filters includes a tapped delay chain and a number of different slices. Each slice has a multiplexer that receives all of the tapped input-signal samples and a programmable current driver. Each slice can be independently programmed to correspond to any one of the taps in the delay chain, such that zero, one, or more slices can be associated with any of the delay-chain taps. Moreover, the current driver in each slice can be independently programmed to contribute any available driver strength level for the selected tap, where the combination of one or more drive strengths associated with a given tap corresponds to the effective tap coefficient for that tap. In this way, the architecture can be programmed to provide a variety of different filters having not just transfer functions with different coefficient values, but also transfer functions having different numbers of pre-cursor and/or post-cursor taps.

Abstract: A near-field communication (NFC) system supports increased data rates using a multiple-input-multiple-output (MIMO) interface. Multiple receive antennas are positioned within the near field of multiple transmit antennas. The NFC system uses a combination of antenna spacing and polarizations to reduce correlation between channels, and thus improves performance by creating closer to ideal MIMO operation. Such system can also be operated as parallel SISO links with reduced cross-channel interference resulting in low power consumption.

Abstract: A method of tracking a second electronic device with respect to a first electronic device is disclosed. The method includes transmitting a first waveform of a first frequency along a first fixed path associated with the first device. A second waveform having a frequency based on the first frequency is wirelessly transmitted from the first device to the second device along a first wireless path. The second waveform is wirelessly transmitted from the second device to the first device along a second wireless path. The first and second waveforms are received at the phase comparator circuit. A first phase relationship of the received first waveform is then compared to a second phase relationship of the received re-transmitted waveform. A coordinate of the second device is determined with respect to a reference coordinate based on the comparing.

Abstract: A digital-analog converter (DAC) comprises a receiving circuit configured to receive an input bit stream and generate a first bit signal stream of the input bit stream, a first delay circuit coupled to the receiving circuit to receive the first bit signal stream and to generate a second bit signal stream representing a delayed version of the first bit signal stream. The DAC also comprises a first current generation circuit to receive the first bit signal stream, the first current generation circuit configured to provide first current, corresponding to the first bit signal stream, to a first output. The DAC further comprises a second current generation circuit to receive the second bit signal stream and to provide second current to the first output responsive to receiving the second bit signal stream, a waveform of the second current inverted and scaled relative to a waveform of the first current.