Abstract: A common mode bias voltage generator apparatus and method includes a plurality of MOSFET-based transistors and a plurality of resistors configured and arranged to provide a half of a supply voltage with a predetermined low output impedance while using relatively little power and circuit area.

Abstract: A method and apparatus for matching common mode output voltage at a switched-capacitor to continuous-time interface. An active continuous time summation circuit is used at the output of the switched-capacitor stage to derive the common mode level that is at the output of the switched-capacitor stage. This derived signal is filtered to remove any noise component remaining in it, and is then used as the reference common mode signal in the continuous time stage. This forces the output common mode, and hence the input common mode of the unity gain amplifier stage, to track the common mode output of the switched-capacitor stage. This adaptive tracking eliminates the common mode interface error, which could be present and could vary from die to die (due to parasitic variations). This technique ensures proper tracking of the DC levels between the negative and the positive terminals of the unity gain amplifier, which is essential for low distortion operation of the amplifier.

Abstract: An offset integrator and method are provided to induce integrator leakage while simultaneously latching and canceling its own offset. The method includes combining a first and second input signals with a part of the output signal of a different polarity to produce a charge signal. An accumulation of the charge signal on a plurality of storage components is used to reduce the offset component of the output signal and simultaneously inducing an integrator leak. A positive and negative components of the input signals are combined with a negative and positive offset components of the part of the output signal, respectively. The method liner includes modifying a positive and negative components of an in-phase and a quadrature signal. A reset signal may be provided to erase a plurality of memory locations. A gating scheme may be used to provide a predetermined signal to produce a two-phase, non-overlapping signal.

Abstract: An FM demodulator circuit with reduced sensitivity to noise and performance nearly identical to theoretical predictions. The FM demodulator is a time sampled detector for binary shift key (BFSK) modulated signals. Its inputs are an in-phase and a quadrature outputs of a receiver, which have been oversampled by a predetermined factor with respect to the data rate. The demodulator circuit differentiates the in-phase and the quadrature input signal by computing the difference between the current signal value and the signal value delayed by one clock period. The differentiated values of the in-phase and the quadrature signals may be changed based on the sign of the quadrature and the in-phase signals respectively to produce modified values of the differentiated in-phase and quadrature signals.

Abstract: A common mode bias voltage generator apparatus and method includes a plurality of MOSFET-based transistors and a plurality of resistors configured and arranged to provide a half of a supply voltage with a predetermined low output impedance while using relatively little power and circuit area.

Abstract: A system operable with any number of different display truth table schemes. The system allows a user to select the truth table scheme and a driver circuit is used to drive either a single or pair of display elements. A binary application select detects a logic 0 if an application sense pin is left floating or is pulled low with a resistor. It detects a logic 1 if the application sense pin is pulled high with a resistor. The sense potential is such that all applications at the pin following reset, namely input or output with connected components will only detect a logic 1 when the pin is pulled high by a pull-up resistor. The output latched application is directed to a responsive circuit operable in a first condition when a logic 0 is detected, and a second condition when a logic 1 is detected. A binary select allows 2n different truth schemes to be selected where n is the number of pins used to select the application. When a first binary code is sensed, a first truth table is implemented.

Abstract: A network device automatically detects the best protocol a network will support. The network device includes a driver for transmitting data, a receiver for receiving data, and a port operationally coupled to the driver and receiver. The network device further includes negotiation logic coupled to the driver and receiver for selecting a protocol in coordination with other network devices. The network device further includes error detection logic and backs down to a lower transmission rate if errors are detected after the initial negotiation of the selected protocol.

Abstract: A security device for use in communications network devices, such as multi-port repeaters, in local area networks to prevent eavesdropping by overwriting the data with an invalid symbol in the data communication packets transmitted to all unintended transceivers connected to the communications network device. Confidential or user sensitive information is not conveyed to the unintended transceivers since the invalid symbol is defined independent of the data. The invalid symbol unambiguously informs the unintended transceivers that the data in the data packet is invalid.

Abstract: A timing recovery circuit is disclosed that prevents phase error over-compensation. The timing recovery circuit includes a phase scanner for determining when phase error over-compensation has occurred and generating a signal for preventing dual phase compensation in response thereto thereby providing an accurate recovered clock signal. The timing recovery circuit also includes a feed-forward equalizer having a plurality of taps providing coefficients for filtering and adapting the input timing recovery circuit to an input signal. The phase scanner compares the tap coefficients to generate signal for preventing phase over-compensation by the feed-forward equalizer. A phase detector is provided for sampling coefficients from the feed-forward equalizer, error signals and output data and generating a phase signal used to generating the recovered clock signal. The signal for preventing phase over-compensation is mixed with the phase signal to generate the recovered clock signal.

Abstract: A method for controlling the power and/or frequency output of a digital data network's transmitters is described. The method controls the transmitter power and/or frequency output by using line loss information as well as the noise margin at both the central office and remote site sides of the transmission link. The transmitters are controlled to minimize the crosstalk between the interconnections on the network. Measurements are taken of the cable losses and signal-to-noise ratios present on the system and the transmitter power and/or frequency are adjusted to minimize unwanted interactions between transceiver pairs on the network.

Abstract: A system and method for calibrating a multi-bit feedback quantizer in a delta-sigma modulation system. A digital data pattern corresponding to a particular DAC code of a multi-bit digital-to-analog converter is transmitted in the transmit channel, where the DAC code is proportional to an analog voltage signal. An effective DC component of the digital data pattern is realized and converted to corresponding digital DC component values. A predetermined number of samples of the digital DC component values are averaged to provide an average sample value. A digital code in the multi-bit feedback quantizer is replaced with the average sample value.

Abstract: A peak detector that compares an input signal to a first reference voltage to produce a maximum sample signal, and compares the input signal to a second reference voltage to produce a minimum sample signal, wherein the maximum and minimum sample signals produce a sampling of the current input signal thereto to produce a maximum output signal and a minimum output signal, respectively. The detector compares the previously retrieved input signal value with a current input signal value. The current input signal is used as the maximum output signal if it is greater than a previous maximum output signal and providing the current input signal as the minimum output signal if it is less than a previous minimum output signal. The output provides signal level and offset signal information which, when gated with a predetermined clock signal, produces nonoverlapping phased output signals.

Abstract: A test signal retiming circuit that captures an input signal to produce a first output signal and generates a second output signal in response to the first output signal and a predetermined reference signal. The second output signal is resistant to an input signal timing variation. A verification is performed to insure the second output signal conforms to timing of a predetermined output signal. The input signal produces the first output signal by acquiring the input signal in a first buffer in response to a first signal and transferring the acquired input signal from the first buffer to a second buffer in response to the first signal. The first output signal is transferred from the second buffer to a third buffer in response to a second signal to produce a second output signal. The second output signal is resistant to a plurality of clock and data skews.

Abstract: A phase-locked loop circuit is disclosed which exhibits a wide capture range and a low quality factor (Q) to prevent ringing and improve stability without adding area, increasing power consumption or increasing noise levels. The phase-locked loop includes a comparator to generate an error signal, an oscillator which generates an output signal in response to a control signal and a loop filter which generates the control signal based on the error signal. The loop filter includes a first integrator operatively coupled through a threshold limit detector to a second integrator. The threshold limit detector supplies an electric charge to the second integrator only when the first integrator is proximate to either an upper limit or a lower limit of the first integrator's operating range. The oscillator generates the output signal which tracks the input reference signal frequency as an integer multiple of the input reference signal frequency.

Abstract: A pulse width distortion correction logic level converter converts differential logic while preserving the pulse width of the original signal. The converter converts a differential input signal to a single-ended signal having a same pulse width as the differential input signal. The present invention receives and converts the differential input signal at a first converter and a second converter, wherein the first converter generates a first output signal, and the second converter generates a second output signal, respectively. Latching the first output signal of the first converter and the second output signal of the second converter produces a full swing single-ended output signal having the same pulse width as the input differential signal. The first output signal sets the latching device with an edge of the first output signal of the first converter and resets the latching device with an edge of the second output signal of the second converter.

Abstract: A 200 Mbps PHY/MAC combination for providing full duplex operation at 400 Mbps is disclosed. The PHY/MAC uses all 4 pairs of wire to create a single channel. A transmit and receive port of a physical layer device is connected to a first end of four pairs of category 5 wiring. A media access control entity sources PLS primitives to manage the flow of frames eight bits a nibble to and from the four pairs of category 5 wiring through the physical layer device. A switch is provided for trunking the four pair of category 5 wiring into a single channel comprising separate 200 Mbps throughput transmit and receive data paths to the physical layer device or into two channels comprising separate 100 Mbps throughput transmit and receive data paths to the physical layer device comprising separate 100 Mbps throughput transmit and receive data paths to the physical layer device.

Abstract: Adaptive equalization methods and adaptive equalizers used with precoded systems dominated by intersymbol interference (ISI) monitor the output of a DFE and compare it to a reference for updating a precoder in response to the comparison.

Abstract: A PHY having a media independent interface (MII) providing connections to a MAC or to another PHY is disclosed. The invention provides a mechanism for connecting a first PHY with a second PHY, wherein the PHY may act as the media access control side of the MII. The system includes a selection means for selecting the mode of operation for the PHY, a MII for providing a synchronous digital interface carrying un-encoded data over separate transmit and receive paths and a translation entity for generating output enables for controlling the flow of the data, wherein the translation entity establishes in response to mode being selected a first flow of data for connecting the PHY to a Media Access Control entity or a second flow of data for connecting the PHY to a second PHY. The translation entity muxes data and control signals based upon the mode selection. A translation synchronization entity is provided.

Abstract: The invention relates in general to error correcting programmable pulse generator, and more particularly to a programmable pulse generator that removes errors due to manufacturing tolerances, power supply variation, and temperature. A method of modifying a signal from a source includes generating a signal and varying a first and second impedance to control the rise and fall time and average level of the signal to produce an output signal, wherein a plurality of voltage levels are modified. Then, varying a first reference current to produce a second reference current that provides a source for a plurality of currents, wherein the plurality of currents includes a first current, a second current and a third current. In addition, scaling the second reference current producing the first current, second current and third current to correct the plurality of modified voltage levels, wherein errors induced by an external environment and manufacturing tolerances are reduced.

Abstract: An efficient implementation of a multirate filter with delayed error feedback prevents an instruction processing rate requirement from increasing by performing interpolation and decimation in a LMS filter element at the same time. The multirate filter calculates an ith coefficient value, wherein i is a set of consecutive integers, by obtaining an (i-1)th error value, obtaining an (i-1)th data value, multiplying the (i-1)th error value and the (i-1)th data value to obtain an ith coefficient product, obtaining Mth coefficient value from a coefficient register, wherein M is a predetermined integer, adding the Mth coefficient value to the ith coefficient product to obtain an ith coefficient value calculating an ith data value by multiplying the (i-1)th data value and the Mth coefficient value to produce ith convolution product, and adding an (i-1)th convolution sum to the ith convolution product to produce an ith convolution sum.