Abstract: An inter-repeater backplane employs both analog and digital circuitry to convey state machine information to adjacent repeaters thereby allowing seamless integration of multiple repeaters into a single hub without requiring additional drivers or external glue logic. A data path allows the passage of data between multiple repeaters on the inter-repeater backplane and an inter-repeater backplane enable allows individual repeaters to take control of the inter-repeater backplane data bus. An inter-repeater backplane driver enables external bus drivers which may be required in synchronous systems with large backplanes. An inter-repeater backplane clock is used to synchronize multiple repeaters on the inter-repeater backplane. Only two leads (IRCOL and IRCFS) are used to provide transmit and receive collision information. These two leads in conjunction with IRENA also indicate which repeater is receiving data.

Abstract: A transconductor-C filter that has coarse and fine control mechanisms allowing for both high speed and high current filtering of the same signal. The filter uses a current controlled oscillator and filter elements that have switchable amplification devices enabling the circuit to adapt to external and internal conditions in real-time. An equalizer is described utilizing the transconductor-C element. Finally, a Phase Locked Loop for providing the control signals to the transconductor-C element is also described.

Abstract: An inter-repeater backplane that may operate in either a synchronous or asynchronous mode for data transmission. The inter-repeater backplane includes a bus of electrical signal conductors coupled between repeaters for communicating electrical signals and data transmission mode detector for determining whether to transmit data synchronously or asynchronously. Data is recovered from a received data packet and is reframed for transmission across the inter-repeater backplane. According to which mode of data transmission is selected, the data is then retimed and transmitted across the backplane. In the synchronous mode of data transmission, the data is synchronized with the system clock. When the asynchronous mode of data transmission is selected, the data is transmitted asynchronously with respect to the system clock. In the asynchronous mode, the recovered data is timed with a clock signal associated with the transmitting repeater.

Abstract: A pair of electrical display elements, LEDs, is driven by a three-state buffer driver circuit. The LEDs have associated current-limiting resistors. The driver circuit applies different selected voltage levels at different selected predetermined frequencies to the LEDs. By having two predetermined frequencies to a pair of LEDs, there can be exhibited at least five different display conditions from the pair of LEDs.

Abstract: A circuit for selecting different applications based upon the manner in which external elements are attached. The selection of the applications is controlled based on the potential detected at a pin immediately following reset. The voltage at a node of the application sense pin is compared with a reference voltage. The pin used to sense the application is used as a sense immediately after reset has occurred. After this it can function as either an output or an input. A flip-flop is connected such that the output of the application sense pin and the condition of reset is directed appropriately to the flip-flop. When the condition of not-in-reset is sensed, the flip-flop latches to a first condition or to a second condition based on the potential at the application sense pin. A binary select allows 2.sup.n different applications to be selected where n is the number of pins used to select the application. When a first binary code is sensed, a first application is implemented.

Abstract: A timing recovery apparatus for recovering the timing from sparse timing information in multi-level or partial response codes. The timing recovery apparatus includes a switch for sampling an incoming line code signal according to a selectable sample rate, a feed forward equalizer for filtering the sampled signal, a decision feedback equalizer for cancelling intersymbol interference in the filtered signal and for recovering the timing in the sampled signal. The timing recovery circuit creates a phase correction signal in response to a signal received from the feed forward equalizer and thereby control the sample rate of the sample switch so that the signal-to-noise ratio at the node before the decision is maximized. The voltage controlled crystal oscillator may be controlled within a certain frequency range by using a second phase detector which compares the phase of the signal controlling the sampling of the incoming line code with a reference clock.

Abstract: An inter-repeater backplane that allows either synchronous or asynchronous data transmission between multiple repeaters integrated into a single hub and enables any repeater to be swapped out without causing the backplane to crash, hang-up, or pass error messages. A dual analog, digital collision signaling scheme is utilized to obviate the need for additional drivers or external glue logic for arbitration. "the specific port of a hub receiving data (PORTN)". and The one port left state (PORTM) information is embedded within the backplane signals. Thus, the backplane scheme according to the present invention is completely seamless. Unique state machines enable the repeater to transmit data either synchronously or asynchronously. In the synchronous mode of data transmission, the data is synchronized with the system clock. When the asynchronous mode of data transmission is selected, the recovered data is synchronized with a clock signal associated with the transmitting repeater.

Abstract: A digital-to-analog (D/A) converter eliminates matching requirements and does not generate harmonics or noise. The D/A converter has an array of injectors for converting an input word to an analog voltage. A plurality of clocked switches discharge the injector array and the feedback path when switched into a first phase position and transfer the injector signal across the feedback path to the output of the D/A converter when switched to a second phase position. The conversion period, the time in which the digital input word is converted to an analog output voltage, is divided into N-1 subperiods. Each injector is enabled once or not at all for each subperiod such that the weighted signal injected during a single conversion period is constant and such that all the injectors in the array contribute an equal amount of signal during a conversion period.

Abstract: A circuit for attenuating phase jitter on an incoming clock signal includes a digital frequency synthesizer, and a phase lock loop including a phase detector. The digital phase detector compares the phase relationship between an incoming signal and a clock signal generated by the digitally controlled frequency synthesizer and produces an output signal proportional to the phase difference. The output signal comprises both a direction indicator and a magnitude indicator for controlling the digitally controlled frequency synthesizer. One of a plurality of phases of a voltage controlled oscillator (VCO) are selected in response to the output signal to alter the frequency of the clock signal.

Abstract: A circuit for comparing transmitted and received data frames containing appropriate stuff symbols to detect when a channel is disconnected. Transmit data symbols consisting of frames of user data, each with a constant number of symbols, are separated by a sequence of symbols known as the frame pattern. At the end of each data frame, just before the next frame pattern, a small number of stuff symbols are added into the frame. The stuff symbols injected in the transmit signal are chosen to be identical to the last scrambled data symbol in the frame of user data. Stuff symbols in a recovered receive signal are chosen to look identical to data symbols which were scrambled at the remote transceiver. A frame-by-frame comparison between the transmit stuff symbols and the next received stuff symbols is carried out on a continual basis.

Abstract: A data communication system employing predetermined equalized waveforms for transmit equalization is disclosed. Serial NRZ data is received from a network controller and utilized to select from memory its equivalent as predistorted and filtered Manchester encoded data. Predetermined waveforms in memory are representative of the analog waveform produced when predistorted digital Manchester encoded data is passed through a high order transmit filter. Data from memory drives a digital to analog converter (DAC) to reconstruct the waveforms into analog form. A line driver having an integrated single pole low pass filter impresses the equalized waveform on to the transmission line.

Abstract: A high frequency receive equalizer for baseband data recovery is disclosed utilizing a frequency selective equalization filter to restore dispersed pulses into a recoverable form. The frequency selective equalization filter has a plurality of independently adjustable stages. Received pulses are passed through an equalization filter whose output is monitored by equalizer feedback control means. The feedback control means adjusts the amount of equalization applied until the amplitude of the equalized pulses reaches a predetermined level.

Abstract: A local area network (LAN) having a 10Base-T media attachment unit (MAU) is disclosed for coupling an attachment unit interface (AUI) to a twisted pair link through an AUI port of the 10Base-T MAU. In addition to meeting or exceeding standards set forth in the proposed supplement (P802.3I/D10) to IEEE standard 802.3 for LANs, the MAU provides an interface between the AUI and a RJ45 (twisted pair) connector which auto-engages when activity is detected on the twisted pair link. Lack of activity on the twisted pair link forces the 10Base-T MAU to isolate its AUI port from the AUI. An Ethernet (coaxial) type MAU commonly connected with the 10Base-T MAU at the AUI may be utilized without manual intervention when the twisted pair link is inactive.

Abstract: A two terminal line driver employing predistortion is disclosed, for driving data over a lossy transmission line such as a twisted pair cable at speeds on upwards of 10 Mbit/s. The driver is designed for voltage output operation wherein fullstep and halfstep information is actively encoded into a voltage level provided for at the output terminals. The driver provides a fullstep voltage spanning the supply rails and a halfstep voltage having a selectable controlled amplitude of a predetermined value. Fat bits resulting from the biphase encoding format are predistorted by dropping the amplitude to a predetermined value, equalizing the relative power content.

Abstract: A phase equalizer in the receiver portion of a bi-directional communication system is disclosed equalizer for reducing precursor intersymbol interference without any substantial degradation in signal to noise ratio. The phase equalizer is implemented as a switched capacitor filter having a clock (switch) rate at least four times the data baud rate and a z-transfer function T(z) of a form: ##EQU1## wherein G, A, and B are fixed but adjustable coefficients.

Abstract: A cost-effective, low power and low distortion digital data line driver is disclosed with the capability to operate from a limited voltage source while maintaining wide output voltage swings. The line driver has the noise immunity attribute of a fully differential input device without all the usual complex CMFB circuitry normally required. The line driver provides a low distortion output with a low output impedance and maintains its impedance value on the same order of magnitude at frequencies up to four times the Nyquist rate.

Abstract: A circuit for attenuating phase jitter on an incoming clock signal includes a digitally controlled oscillator, a phase lock loop including a phase detector, and a dithering circuit. The oscillator is capable of generating N discrete frequencies selectable through digitally controlled inputs controlling switched, capacitively-loaded amplifier stages. The phase lock loop provides a total of C.times.N.times.NB frequencies. The phase detector consists primarily of an up/down counter with an overflow/underflow limiter circuit. The dithering circuit modulates the oscillator signal to reduce inadequate rejection behavior when the incoming clock frequency is substantially the same as one of the N selectable frequencies of the oscillator divided down to match the frequency of the incoming clock.

Abstract: A timing recovery loop comprising a multi-point sampling phase comparator 10, a data independent smoothing filter 12, a command sequencer 14, a digitally controlled ring oscillator with clock phase selection 16, a clock divider 18, a sampling clock generation control 20, a bandwidth controlling filter 166, a sequential prioritizer 168, a quarter bit detector 170, and a filter 172. The timing recovery loop has a triple loop structure for improved jitter tolerance and bandwidth control. All three loops share the common components of the ring oscillator 16, the clock divider 18, the sampling clock generation 20, the sampling phase comparator 10, and the command sequencer 14. The remaining components are used among one or more of the loops.

Abstract: An adaptive convergent decision feedback equalizer apparatus and method is disclosed for reducing intersymbol interference (ISI) in a data communication system. ISI is cancelled by generating and subtracting an estimation of the interference from a received signal. the estimation is generated by a N-tap transversal filter in which individual delayed received signals stored in the taps are multiplied by the respective adaptable tap coefficient and summed to form a digital representation of the ISI present. The present invention takes two steps to reduce the probability of coefficient adaptation from diverging. First, the DFE performs a coefficient modification only when the delayed received signal is a particular filter tap is a maximum or minimum level of the selected line code. A second step to eliminate divergence addresses the start up coefficient determination and errors in ISI estimation as the filter coefficients grow in size.

Abstract: An adaptive balancing network apparatus provides improved cancellation of transhybrid response. The adaptive balancing network removes near-end echo much better than the prior art methods over a wide variation of the loop plant, and hence, provides a cost-effective implementation of a transceiver. The apparatus comprises two adaptive balancing networks and a balancing network filter that provides increased echo cancellation in the analog domain of up to 25 dB, so that the signal can be amplified before the A/D and D/A conversion by about 20 dB more than it could be by a simple divider balancing network. Therefore, the requirements for A/D and D/A convertors can be relaxed from 13 bits to 10 bits (or less). The first adaptive balancing network removes a first portion of the echo using a transmitted signal. The balancing network filter reshapes the transmitted signal and shifts it in time so that the second adaptive balancing network can cancel a second portion of the echo.