Abstract: A method and apparatus for echo cancelling linear and nonlinear echo components from a received signal by temporally and spatially separating the overall echo canceller into a fast, transversal filter based linear echo canceller which quickly cancels the linear echoes and a slow, look-up table based nonlinear echo canceller which cancels the nonlinear echo components.

Abstract: A transversal filter apparatus having a shift register, an averaging circuit for averaging data stored in sequential shift registers, and a multiplier for multiplying the averaged data. Additionally, a method and apparatus for echo cancelling a transhybrid response having a well behaved portion by using a transversal filter based echo canceller wherein the data stored in adjacent registers of the shift register which correspond to the well behaved portion of the transhybrid response are averaged together prior to being applied to a multiplier. This apparatus and method makes possible a reduction in the amount of hardware required to achieve a given level of echo cancellation.

Abstract: A device (16) for reducing the intrinsic low frequency jitter within a Digital Phase lock loop (17). A Digital Phase lock loop high speed clock signal (4) is produced by a multistage oscillator (5), producing a plurality of identical frequency signals, each differing in phase. An adjust signal (18) generated by the Digital Phase lock loop output clock signal (3) causes an adjacent phase angle to be selected as the high speed clock signal (4), thereby reducing the period of the clock signal (4) and, in effect, accelerating the high speed clock signal (4). The current state of the selected phase and the appropriate selection of adjacent phase is monitored by a ten stage shift register (20-29), the presence of a "high bit" within a particular shift register block causing selection of the individual phase (6-15) which serves as the input to that particular shift register stage. An error correction circuit (40) detects the presence of more or less than a single high bit within the shift register stages (20- 29).

Abstract: A digitally controlled timing recovery loop is comprised of a digitally controlled Phase Locked Loop (PLL) consisting of a phase detector, loop filter, and voltage controlled oscillator (VCO). The phase detector is a multi-point sampling phase comparator. The loop filter is comprised of a data independent smoothing filter and a command sequencer. The VCO is a digitally controlled ring oscillator with clock phase selection. The timing recovery loop tolerates a relatively large amount of incoming jitter and minimizes data dependent, ISI-induced, intrinsic jitter.

Abstract: A phase locked loop configured as a frequency multiplier capable of nonintegral feedback path division utilizes a multiphase voltage controlled oscillator (5) which generates a plurality of signals (10a-10f) having a substantially identical frequency but each offset equally from the other by a given phase angle. A commutator (3) selects signals of adjacent phases so as to give the time average output signal (9) a frequency higher or lower than the frequency 10a-10f. Frequency translation is accomplished by periodically selecting signals having a longer or shorter period as desired so that a commutator output signal (9) is delayed or advanced by an appropriate amount. In the preferred embodiment, the phase locked loop is capable of converting a 1.544 MHz signal to a 2.048 MHz signal or vice versa.

Abstract: An all-digital phase-locked loop (ADPLL) is disclosed having a wide bandwidth while maintaining relatively small steps for phase error correction. A random walk filter with memory and a pattern sensitive phase adjustment circuit cooperate to control the ADPLL frequency/phase adjustment rate by taking multiple, relatively smnall steps in phase error correction at fixed intervals of time. A short cycle occurs when the phase disparity is large, interrupting the execution of the fixed interval cycle expediting the ADPLL phase lock time without sacrificing resolution in the phase error correction steps.

Abstract: A current-controlled oscillator includes a plurality of switches for generating a time delay signal, each switch including an MOS transistor operatively coupled to the next gate by means including a capacitor, the final MOS transistor being connected to the initial MOS transistor by a feedback conductor also operatively connected with a capacitor. The frequency of the oscillator is varied by varying current injected into the oscillator.

Abstract: A phase locked loop circuit includes a phase detector and an oscillator associated therewith, and a voltage-to-current converter for providing that lag signals sent thereto from the phase detector provide increased signal to the oscillator, and lead signals sent thereto from the phase detector provide decreased signal to the oscillator.