Abstract: A low noise amplifier circuit provides high gain and an input impedance matching a source output impedance by combining two amplifiers having different operational characteristics in parallel. The amplifier circuit includes a first amplifier having an input impedance matching a source and a gain less than a system requirement and a second amplifier having a gain meeting the system requirement and an input impedance substantially higher than the input impedance of the first amplifier, the second amplifier being connected in parallel to the first amplifier. The first amplifier includes an input and an output and the second amplifier includes an input and an output, the input to the first amplifier and the input to the second amplifier being connected to the source. A summer is provided for combining an output signal from the first amplifier with an output of the second amplifier.

Abstract: An offset-removing gain circuit where the detected offset is independent of the gain of the circuit. The gain circuit includes a differential amplifier transfer circuit with an input and a output, an integrator connected to the output of the differential amplifier transfer circuit through a first impedance, and a second impedance connecting an output of the integrator to the input of the differential amplifier. The impedances may include resistors, capacitors or combinations thereof. The circuit may further include a switched capacitor circuit, where a plurality of capacitors are connected between input and output terminals using switches, whereby the capacitance of the switched capacitor circuit is altered by the switches to remove offset at the integrator output without changing the frequency response thereof.

Abstract: A state synchronized cipher text scrambler is disclosed. The state synchronized cipher text scrambler enables multiple data streams to be scrambled in parallel in such a way that the data streams are uncorrelated with respect to each other and there is a large fixed delay relationship between the scrambler bits over the multiple streams. This enables a receiver to correctly identify the ordering of the multiple data streams with respect to each other automatically, correct for any polarity or wire-swap misconnections and align the received multiple data streams despite differential delays between the data streams.

Abstract: A system for integrating multiple repeaters into a single collision domain employs both analog and digital circuitry to convey system-wide collision information to repeaters thereby allowing seamless integration of multiple repeaters into multiple hubs without requiring additional drivers or external glue logic. One signal line (CFSL) within each hub is used to aggregate collision information within the hub. Further, only one signal line (CFSS) is used to aggregate collision information between hubs. This latter signal line in conjunction with two intra-hub signal lines (COLZ and SNGLZ) distributes system-wide collision information to all of the repeaters in all of the hubs.

Abstract: A gigabuffer repeater transmission protocol minimizes the amount of buffering necessary at the repeater. Minimum buffer memory requirements are accomplished by using the initial portion of the data packet as the "Request to Send" message and waits, if necessary, until it receives a "Clear to Send" signal from the repeater. Thus, the repeater retains the majority of the buffering at the source of the data, where it is typically cheapest. Further, the repeater transmission scheme can be applied to centrally arbitrated repeaters.

Abstract: A packetized trellis coder and method for providing error correction coding of IEEE 802.3 frame formatted Ethernet packets for transmission at one gigabit per second (Gbps) over twisted-pair wiring. The error correction code protects each byte of the ethernet frame with a parity bit constructed using a convolutional encoder such that a maximum likelihood sequence estimation at the receiver using a Viterbi decoder will result in a significant receiver performance gain. At the end of the Ethernet packet, the trellis coder restores the states of the convolutional encoder to a known value (state 0) before beginning Idle transmission so that the Viterbi decoder at the receiver can read off the end-of-packet symbols without any performance penalty. The mapping and the inverse mapping from raw data bits to symbols and vice-versa can be implemented with simple gates due to algorithmic symbol mapping of a 4-D trellis code via 1-D partitioning.

Abstract: A baud rate sampling receiver, for reducing signal overshoot and improving equalization of a communications channel. The receiver filters an input signal, samples the filter output signal at the baud rate, continuously monitors the filter output signal for overshoot using a latching comparator circuit, and controls filter parameters based upon the sampling and monitoring using a filter control. The latching comparator circuit includes a positive latching threshold comparator circuit and a negative latching threshold comparator circuit. Each of these comparator circuits provides a threshold control bit to the filter control in response to a detection of signal overshoot. While the filter control also receives information about the filtered output signal from a sampling circuit, the threshold control bits indicate to the adaptive filter control immediately, rather than at the next sample point, when signal overshoot is present.

Abstract: A method of performing motion estimation is disclosed which reduces the memory bandwidth requirements and simplifies the computations for performing block matching. First, multibit pixel values of frames are converted to single bit pixel values. Then, a previous frame of single bit pixel values and a reference frame of single bit pixel values are stored. To find a best match block in the previous frame, sum-of-absolute differences of pixel values between the reference frame and a block in a search area within the previous frame are compared. Finally, a motion vector representing the difference between the reference block and the best matched block in the previous frame is calculated. The value of a reference pixel is thresholded with respect to a low-pass filtered average value around the reference pixel. The reference pixel is substituted by the average value of the neighboring pixels. The multibit pixel values may be eight bit intensity values.

Abstract: A security device for use in communications network devices, such as multi-port repeaters, in local area networks to prevent eavesdropping by overwriting the data with an invalid symbol in the data communication packets transmitted to all unintended transceivers connected to the communications network device. Confidential or user sensitive information is not conveyed to the unintended transceivers since the invalid symbol is defined independent of the data. The invalid symbol unambiguously informs the unintended transceivers that the data in the data packet is invalid.

Abstract: A state synchronized cipher text scrambler is disclosed. The state synchronized cipher text scrambler enables multiple data streams to be scrambled in parallel in such a way that the data streams are uncorrelated with respect to each other and there is a large fixed delay relationship between the scrambler bits over the multiple streams. This enables a receiver to correctly identify the ordering of the multiple data streams with respect to each other automatically, correct for any polarity or wire-swap misconnections and align the received multiple data streams despite differential delays between the data streams.

Abstract: A low power line driver uses a dynamic biasing scheme together with single ended architecture to achieve low power, fast speed and high return loss. The line driver includes a first and second operation amplifier each having an output port for generating an output pulse signal having a rising and falling edge. The load is coupled to the first and second output port by a transformer. A first and second digital control circuit is coupled to the first and second operational amplifiers to control the operational amplifiers. The first and second operational amplifiers further include a pulse circuit for generating the output pulse signal and a selectable current source having a first mode for injecting a high current to the pulse circuit to provide a high slew rate for the rising edge of the output pulse signal and a second mode for injecting a second current to the pulse circuit during the generation of the remaining portion of the output pulse signal.

Abstract: A communications inter-repeater circuit that includes an Attachment Unit Interface (AUI) port which can be selectively switched between a Media Attachment Unit (MAU) mode and a Data Terminal Equipment (DTE) mode. This selective change in the AUI allows for direct connection of Data Terminal Equipment (DTE) to the repeater without requiring a separate MAU. The determination of the mode for the AUI port is made by a selector. The selector may be a configuration sense pin whereon a selection potential is applied during reset of the repeater functions.

Abstract: A Physical Layer Device is disclosed having power savings features operable during auto-negotiation for multiple technologies. Excessive power consumption is alleviated by decreasing the power required by the receiver(s) during parallel detection. The Physical Layer Device includes at least one port, with each port including a parallel detection receiver for receiving data and messages from a connected device, the data and messages including autonegotiation fast link pulses indicating a technology capability of the connected device, a cycler for enabling the parallel detection receiver for a fraction of an autonegotiation period and a controller for controlling the cycler. The enabling of the receiver for each port, whether a multiple or single port device, is staggered to prevent more than one receiver from being enabled at one time.

Abstract: The analog adaptive equalizer provides convergence of an error signal by decoupling the error canceller, the automatic gain control and the filter to provide truly adaptive error minimization. The invention includes an automatic gain control (AGC) circuit for providing broadband amplification of an input signal to generate an AGC output signal, a filter for receiving the AGC output signal and providing high frequency signal conditioning to generate a filter output signal, an error detection circuit for generating an error signal representing the difference between the filter output signal and an expected output signal and a calculator for receiving the error signal and providing a gain correction signal to the automatic gain circuit to adjust the gain of the automatic gain circuit and a filter control signal to adjust the filter range of the filter, the gain correction signal and the filter control signal being used to cancel the error signal.

Abstract: A packetized trellis coder and method is disclosed for providing error correction coding of IEEE 802.3 frame formatted Ethernet packets for transmission at one gigabit per second (Gbps) over twisted-pair wiring has been disclosed. The error correction code protects each byte of the ethernet frame with a parity bit constructed using a convolutional encoder such that a maximum likelihood sequence estimation at the receiver using a Viterbi decoder will result in a significant receiver performance gain. At the end of the Ethernet packet, the trellis coder restores the states of the convolutional encoder to a known value (state 0) before beginning Idle transmission so that the Viterbi decoder at the receiver can read off the end-of-packet symbols without any performance penalty. The mapping and the inverse mapping from raw data bits to symbols and vice-versa can be implemented with simple gates due to algorithmic symbol mapping of a 4-D trellis code via 1-D partitioning.

Abstract: A scalable high performance ATM cell/packet switch (HiPAS) element for a shared memory switch fabric application. The switch element includes a PAC Bus (Packet/ATM Cell Bus) and the Switch Fabric Controller bus (SC Bus). The HiPAS switch element receives and transmits the ATM cells/packets through the PAC Bus. The PAC bus provides independent parallel datapaths for the receive port and transmit port. The PAC Bus provides a unique structural feature to the HiPAS switch element and allows expansion to the switch capacity in a manner similar to a bit-slice processor. Multiple number of HiPAS switch elements can be concatenated to expand the capacity. In the concatenated configuration, the datapaths of the receive port and transmit port are interleaved so that the interconnection remains point-to-point. As the result, all of the switch ports in the switch execute the cell transactions concurrently on the PAC bus.

Abstract: An inter-repeater backplane that allows seamless integration of multiple repeaters into a single hub and wherein each repeater may be swapped out without causing the backplane to crash, hang-up or pass error messages. The mixed signal state machines operate in conjunction with the dual analog, digital collision signaling scheme so that repeaters can be removed from the hub without causing the remaining repeaters in the hub to malfunction. Additional drivers or external glue logic are not needed for arbitration because PORTN and PORTM information is embedded within the backplane signals. Thus, the backplane scheme according to the present invention is completely seamless.

Abstract: A system which uses per-port last source address registers, which are part of the repeater function, for making filtering/forwarding decisions, which are part of the bridging function. The system includes a single repeater collision domain divided into segments, one or more transceivers for each segment, a master management device/bridge for the first segment, and one or more slave management devices for the remaining segments. A local signal which allows the forwarding/filtering decision to be distributed is attached to the master management device and all slave management devices. A remote bridge interface is attached to the master management device. A management interface for each management device, either master or slave, is used to attach each management device to its respective transceiver for the ports which controlled by the management device.

Abstract: A method and apparatus for implementing a two-port Ethernet bridge using a semaphoring technique. The Ethernet bridge includes two MAC devices, a bus, a memory and a semaphoring scheme. The controllers include a first address which is used for indicating receipt of the packet and a second address which is used for indicating the transmission of the packet from the memory and for clearing of the memory location of the packet for further use. The receiving media access controller receives a data packet on a first port and the transmitting media access controller transmits the packet from the memory to a second port associated with the address of the intended user designated by the packet. The memory includes a dual-ring structure, with one ring used for receive traffic and the other ring used for transmit traffic. The MACs also include programmability for designating the type of packets that may be received.

Abstract: A system consisting of a repeater management function and media access control into a single device. The repeater management functions and the media access control may also be combined with bridging support functions. The repeater management function uses a repeater management interface to control information transferred to an access port and to control repeater functions under direction of access port and monitor repeater function and provide status via access port and to control the bridge support function. The bridge function controls information transferred through a bridge port. The MAC function transfers information between the repeater data port and the MAC port (transmit/receive). The integration of the media access controller and repeater management into a single device is independent of the implementation of any of the ports.