Abstract: A DC/DC converter and a method protect a MOSFET driven by the converter from overcurrent conditions. No extra pins are required to sense the current, which saves IC package area and cost.

Abstract: A differential current steering (CS) circuit uses feedback from the differential output nodes A and B to cause current steering devices (e.g., MOSFETs) to effectively exhibit an infinite output impedance when conducting. Therefore, the signal on the output nodes A or B does not significantly change the voltage at the common node, This is particularly useful when the differential output nodes are connected to differential output buses in a digital-to-analog converter. The circuit dynamically cancels, though feedback, the signal induced at the common node by the signal present at the “steered” output node. Therefore, the CS circuit effectively presents an infinite output impedance between the common node and the output nodes. In some cases, it may be desirable to not create a substantially infinite output impedance for the CS circuit but control the impedance to a predefined level to counter other distortions in the system.

Abstract: A current source is switchable between two precisely defined output currents. A terminal of a coupling capacitor is coupled to the gate of an output MOSFET. The other terminal of the capacitor is switched between two reference voltages to toggle the output MOSFET to output the selected one of the two currents. A switchable bias voltage source is coupled to the gate only during the on state of the output MOSFET to set the gate voltage of the output MOSFET. The current output of the current source is quickly and accurately changed. A reference MOSFET is not directly coupled to the output MOSFET, so there are no slow settling components coupled to the gate of the output MOSFET.

Abstract: In one embodiment, a temperature compensation circuit is used in a peak current control multi-phased DC/DC converter. Each phase has a duty cycle needed to generate a regulated output voltage of the converter. The temperature for each phase in the converter is sensed to generate corresponding first signals for all the phases. The first signals are averaged to generate a second signal corresponding to the average temperature of all the phases. For each phase, a third signal is generated corresponding to the difference between the first signal and the second signal. The third signal is then used to adjust the duty cycle of each phase to control the temperature of each phase to be substantially equal to the average temperature. In the steady state, the output voltage of the converter will be the desired voltage and the temperatures of the phases will be balanced.

Abstract: Circuits and methods for maintaining a substantially constant input and output current for a charge pump circuit are provided which reduce current variation during switching intervals. The charge pump circuitry of the present invention maintains a current flow path from a current source to the charge pump output which minimizes or eliminates spikes normally associated with the switching intervals.

Abstract: Methods and systems for analog to digital converter and systems incorporating the same are provided. Specifically, an analog sampler that has a reduced input current is disclosed. According to the present teaching, an apparatus for sampling an input voltage includes a first switch having its first terminal connected to an input voltage, and a first pre-charging circuit, coupled to a second terminal of the first switch, that provides a first pre-charged voltage that is substantially equal to the input voltage. The first pre-charged voltage is provided at the first terminal of the first switch before the first switch is turned on. The apparatus further includes a second pre-charging circuit coupled to both the first pre-charging circuit and the second terminal of the first switch, where the second pre-charging circuit charges the first pre-charged voltage prior to the first switch being turned on.

Abstract: Novel circuitry and methodology for operating a multiple channel switching regulator system to extend an input to output voltage ratio by setting individual constant switching frequencies to switching regulator channels. In the switching regulator system having at least first and second switching regulators, a first clock circuit supplies a first clock signal at a first clock frequency to define a switching frequency of one of the first and second switching regulators. A second clock circuit is synchronized to the first clock signal for producing a second clock signal at a second clock frequency different from the first clock frequency, to define a switching frequency of the other of the first and second switching regulators.

Abstract: An embodiment of an analog-to-digital converter system is described wherein an analog voltage signal Vin(t) is provided by an input amplifier. The analog signal Vin(t) has a predetermined full-scale range that is less wide than a reference voltage (Vref) range used by a downstream ADC to derive a first digital (numerical) representation D1(k) of a sampled value Vin(k) of the analog signal Vin(t). The first digital representation has N bits. A digital circuit then converts the N-bit D1(k) code to a second numerical representation D2(k) of the sampled analog voltage Vin(k) with respect to the full-scale range of the ADC system. The D2(k) code has P bits of resolution, which may be less than N bits. The P-bit D2(k) code representing Vin(k) is the output of the ADC system. Therefore, the width of the reference voltage range applied to the ADC is greater than the width of the system's full-scale range at the output of the system.

Abstract: Apparatus and method for a limiting amplifier with improved phase noise. The improved limiting amplifier includes an input port, an output port, and one or more cascaded gain stages. The input of a first gain stage is connected to the input port of the limiting amplifier. The output of a last gain stage is connected to the output port of the limiting amplifier. Among the cascaded gain stages, an output of each gain stage is connected to an input of an adjacent gain stage. Each gain stage i, 1<i<n?1, is configured so that it is capable of selecting at least one lowpass filter corner frequency ?pi, and thereby reducing the phase noise of the gain stage through the broadband noise reduction for frequencies greater than ?pi. Here, ?pi is selected from a plurality of values associated with the gain stage to optimize the phase noise of the limiting amplifier by trading off reducing the broadband noise of the gain stage versus maintaining a sufficient output slew-rate of the gain stage.

Abstract: A powered LED circuit may include a power supply configured to generate and deliver an output current at a controllable average value with a substantial ripple component, one or more LEDs connected together, and a ripple reduction circuit connected to the power supply and to the one or more LEDs. The ripple reduction circuit may have a current regulator connected in series with the one or more LEDs which is configured to substantially reduce fluctuations in the current which flows through the one or more LEDs due to the ripple component of the output current, but not fluctuations in the current which flows through the one or more LEDs due to changes in the average value of the output current.

Abstract: A synchronous boost DC/DC conversion system comprises an input for receiving a DC input voltage, an output for producing a DC output voltage, a power switch controllable to adjust an output signal of the conversion system, and an inductor coupled to the input. A synchronous rectifier is configurable to create a conduction path between the inductor and the output to provide the inductor discharge. A control circuit is provided for controlling the synchronous rectifier as the input voltage approaches the output voltage, so as to adjust average impedance of the conduction path over a discharge period of the inductor.

Abstract: An actual linear amplifier distorts an input signal, such as an RF signal, and generates third order intermodulation (IM3) products. In an embodiment of a Class A amplifier, the linear amplifier is a bipolar, common emitter-configured (CE) transistor using a cascode transistor to provide a fixed collector bias voltage to the CE transistor. The CE transistor has a transconductance vs. base-emitter voltage (VBE) characteristic which, when plotted, shows a transconductance that increases with an increasing VBE to a maximum, then drops, then tapers off, wherein there is an inflection point between the maximum transconductance and where the transconductance tapers off. A DC bias circuit provides a DC bias voltage to the base of the CE transistor that causes the CE transistor's operating point to track the inflection point over a range of temperatures. This operating point causes the IM3 products to be greatly reduced.

Abstract: An actual linear amplifier distorts an input signal, such as an RF signal, and generates third order intermodulation (IM3) products. A single-port predistortion circuit is connected at a single node of an input line to the amplifier via an AC coupling capacitor. The fundamental frequency of the input signal is applied to a forward biased diode junction. The current through the diode is applied to a second capacitor. The appropriate setting of a tuning device, such as a tunable resistor or a tunable capacitor, causes the predistortion circuit to invert the second harmonic generated by the diode. The inverted second harmonic signal is applied to the single node of the input line to add predistortion to the signal applied to the amplifier. The predistortion cancels or substantially reduces the IM3 products at the output of the amplifier.

Abstract: A differential current steering (CS) circuit uses feedback from the differential output nodes A and B to cause current steering devices (e.g., MOSFETs) to effectively exhibit an infinite output impedance when conducting. Therefore, the signal on the output nodes A or B does not significantly change the voltage at the common node, This is particularly useful when the differential output nodes are connected to differential output buses in a digital-to-analog converter. The circuit dynamically cancels, though feedback, the signal induced at the common node by the signal present at the “steered” output node. Therefore, the CS circuit effectively presents an infinite output impedance between the common node and the output nodes. In some cases, it may be desirable to not create a substantially infinite output impedance for the CS circuit but control the impedance to a predefined level to counter other distortions in the system.

Abstract: A circuit may sense the differential voltage across two nodes that each have a non-zero common mode voltage. The circuit may have a positive input impedance that is imposed across the nodes. An impedance compensation circuit may generate a compensation current that is delivered to the nodes that substantially cancels the loading effect of the positive input impedance. The impedance compensation circuit may generate a negative input impedance that is imposed across the two nodes that is substantially the same as the positive input impedance. The impedance compensation circuit may instead be configured to deliver the compensation current to the nodes.

Abstract: An efficiency measuring circuit may measure the efficiency of a DC-DC converter having a switching inductor with an internal DC resistance and a plurality of electronic switches that control current through the inductor. A duty cycle circuit may measure the duty cycle of current flowing through one of the electronic switches. A current sense circuit may measure the current flowing through one of the electronic switches. An inductor voltage sensor circuit may measure the voltage across the inductor. A computation circuit may compute the internal DC resistance of the switching inductor based in part on the duty cycle measured by the duty cycle circuit and the current measured by the current sense circuit. The computation circuit may also compute the efficiency of the DC-DC converter.

Abstract: An error amplifier may be part of a voltage regulator and may include a single feedback input configured to receive a feedback signal. A single error output may be configured to provide an error output signal indicative of error in the feedback signal. A comparison circuit may be configured to provide an error signal to the single error output which is indicative of a difference between the feedback signal and whichever one of a set of reference signals is closest to the feedback signal. One or more of these reference signals may each be derived from an offset from a ground reference. One or more of the other reference signals may each be derived from an offset from a non-ground reference, such as a source of power for the error amplifier. The error amplifier may be on a single integrated circuit along with an associated driver circuit.

Abstract: A power supply system has an inductive device, a plurality of switching devices for providing connection of the inductive device to input and output nodes and a ground node, and a switch driver circuit for driving the switching devices so as to enable the power supply to operate in a boost mode to increase the input voltage, in a buck mode to decrease the input voltage, and in a solid-state flyback mode to transfer between the boost mode and the buck mode. In the solid-state flyback mode, the switching devices are controlled to provide switching of the inductive device between an input state in which the inductive device is connected between the input node and the ground node, and an output state in which the inductive device is connected between the ground node and the output node.

Abstract: A semiconductor device such as a field-effect transistor, improved to reduce device resistance, comprises a leadframe which includes a die paddle integral with a first set of leads and a second set of leads that is electrically isolated from the first set, a semiconductor die having its lower surface positioned on, and electrically connected to, the die paddle, and a conductive layer on the upper surface of the die. At least one electrically conductive wire, preferably plural wires, extend laterally across the second surface of the semiconductor die, are in electrical contact with the conductive layer, and interconnect corresponding second leads on opposite sides of the die. The plural wires may be welded to leads in succession by alternate ball and wedge bonds on each lead. The conductive layer may be an aluminized layer on which is formed a thin layer a solderable material, such as tin. A solder is deposited on the tin layer, enmeshing the wires.

Abstract: An apparatus and method for dimming a light emitting diode (LED) driver. The apparatus includes a triode alternating current (TRIAC) dimmer and an LED driver receiving an input voltage from an output of the TRIAC dimmer so that the state of the LED driver is controlled by the TRIAC dimmer. The LED driver includes an active damping circuit configured for damping, upon detecting a rising edge of a bridge rectified input voltage, resonance caused by the TRIAC dimmer and the LED driver for a fixed period of time.