Abstract: In one embodiment, a current sensing circuit corrects for the transient and steady state temperature measurement errors due to physical separation between a resistive sense element and a temperature sensor. The sense element has a temperature coefficient of resistance. The voltage across the sense element and a temperature signal from the temperature sensor are received by processing circuitry. The processing circuitry determines a power dissipated by the sense element, which may be instantaneous or average power, and determines an increased temperature of the sense element. The resistance of the sense element is changed by the increased temperature, and this derived resistance Rs is used to calculate the current through the sense element using the equation I=V/R or other related equation. The process is iterative to continuously improve accuracy and update the current.

Abstract: The most significant portion of a digital word may be converted into a high and a low analog voltage representative, respectively, of the highest and lowest possible values which a digital word could have with the most significant portion. An analog output may be produced by interpolating between the high and the low analog voltage in accordance with the value of the least significant portion of the digital word. A differential transconductance input stage may have pairs of differential input transistors. For each differential input transistor pair, a separate bias current circuit may provide a bias current to the differential input transistor pair, separate from the bias current provided to the other differential input transistor pairs. All bias current circuits may be identical in a linear interpolator. The transconductance input stage may have a gain of at least 20 dB and may result in an integral non-linearity in the analog output of no more than 0.

Abstract: A system for and method of providing a signal proportional to the absolute temperature of a semiconductor junction is provided. The system comprises: a preprocessing stage configured and arranged so as to process a signal from the semiconductor junction so as to produce a preprocessed signal including a resistance error term; and a temperature to voltage converter stage for converting the preprocessed signal to a voltage proportional to absolute temperature representing the absolute temperature of the semiconductor junction; wherein the system is configured and arranged so as to remove the resistance error term so as to produce a resistance error free signal representative of the semiconductor junction temperature.

Abstract: An analog-to-digital converter (ADC) system and method. The ADC system includes a digital control circuit, an amplifier, a capacitor, and an evaluation circuit. The digital control circuit is configured to sequentially configure the ADC system in a first configuration and a second configuration to derive a digital representation of an analog signal value. The amplifier circuit includes an amplifier input terminal and an amplifier output terminal. The capacitor has a first capacitor terminal coupled to the amplifier input terminal in the first and second configurations of the ADC system. The capacitor further has a second capacitor terminal coupled to the amplifier output terminal in the first configuration of the ADC system. The evaluation circuit is configured to provide a first digital code to represent a first voltage level at the amplifier output terminal in the first configuration of the ADC system.

Abstract: A circuit may include a source of electrical energy and a plurality of current loads. Each load may be of a different amount. For each current load, a resistance may be in series between the source and the current load. The resistance may be weighted inversely proportional to the amount of the current load with respect to the other resistances. For each resistance, an integrator may generate an integrated output representative of an integration of the current traveling through the resistance. A summer may generate a summed output which is representative of the sum of each of the integrated outputs, weighted inversely proportional to the resistance that is associated with the integrated output.

Abstract: A device having a signal level different from a signal level of an external device includes an interface, such as an I2C interface, for providing communications with the external device. The interface is configurable to support communications with the external device either via multiple wires or via a single wire.

Abstract: A circuit for charging a capacitor block including series-connected capacitive elements has an input node for receiving an input, an output node coupled to the capacitor block, a third capacitive element connectable to the input node and the output node, and first and second switching circuitries coupled to the third capacitive element. A voltage sensor determines a relationship between first voltage at the first capacitive element and second voltage at the second capacitive element to separately control switching of the first and second switching circuitries in accordance with the relationship between the voltages.

Abstract: A pulse width modulation circuit may generate an adjustable output signal that periodically transitions between a first and a second state with an adjustable duty cycle. A first pulse generator circuit may be configured to generate a first pulse signal that periodically transitions at an adjustable delay with respect to a periodic reference signal. A second pulse generator circuit may be configured to generate a second pulse signal that periodically transitions at an adjustable delay with respect to the periodic reference signal. A logic circuit may be configured to generate the adjustable output signal based on both the first and the second pulse signals.

Abstract: A switch mode converter converts an input DC voltage applied at one level at the converter input to an output DC voltage at a second level at the converter output. A switch is arranged to switch the input DC voltage on and off during each cycle of a plurality of cycles. An energy storage unit temporarily stores energy from the input source voltage when the switch is on, and releases energy when the switch is off during each cycle. Input energy stored is equal to the energy released with each cycle and achieves equilibrium when the converter is operating into normal loads. A reset mechanism provides additional reset voltage during each cycle to achieve equilibrium when the converter is operating in a fault condition.

Abstract: A circuit for charging a capacitor block including series-connected capacitive elements has an input node for receiving an input, an output node coupled to the capacitor block, a third capacitive element connectable to the input node and the output node, and first and second switching circuitries coupled to the third capacitive element. A voltage sensor determines a relationship between first voltage at the first capacitive element and second voltage at the second capacitive element to separately control switching of the first and second switching circuitries in accordance with the relationship between the voltages.

Abstract: An apparatus for driving a light emitting diode (LED). A rising edge of a pulse width modulation (PWM) signal is first sensed. Upon sensing the rising edge, a threshold pulse (TP) signal is initiated that has a configured width started when the rising edge is sensed, an LED current with an amplitude at a previously set level is generated, and starting to charge a capacitor which yields a voltage Vcap. Subsequently, a falling edge of either the PWM signal or the TP signal is detected. Upon detecting the failing edge, the circuit stops charging the capacitor, samples, after a first delay from the detected falling edge, the voltage Vcap, and adjusts a level of the amplitude of the LED current based on the sampled voltage Vcap. When the falling edges of both the PWM and TP signal are detected, the LED current is terminated.

Abstract: An actual linear amplifier distorts an input signal, such as an RF signal, and generates third order intermodulation (IM3) products. A single-port predistortion circuit is connected at a single node of an input line to the amplifier via an AC coupling capacitor. The fundamental frequency of the input signal is applied to a forward biased diode junction. The current through the diode is applied to a second capacitor. The appropriate setting of a tuning device, such as a tunable resistor or a tunable capacitor, causes the predistortion circuit to invert the second harmonic generated by the diode. The inverted second harmonic signal is applied to the single node of the input line to add predistortion to the signal applied to the amplifier. The predistortion cancels or substantially reduces the IM3 products at the output of the amplifier.

Abstract: An actual linear amplifier distorts an input signal, such as an RF signal, and generates third order intermodulation (IM3) products. In an embodiment of a Class A amplifier, the linear amplifier is a bipolar, common emitter-configured (CE) transistor using a cascode transistor to provide a fixed collector bias voltage to the CE transistor. The CE transistor has a transconductance vs. base-emitter voltage (VBE) characteristic which, when plotted, shows a transconductance that increases with an increasing VBE to a maximum, then drops, then tapers off, wherein there is an inflection point between the maximum transconductance and where the transconductance tapers off. A DC bias circuit provides a DC bias voltage to the base of the CE transistor that causes the CE transistor's operating point to track the inflection point over a range of temperatures. This operating point causes the IM3 products to be greatly reduced.

Abstract: A circuit may include a source of electrical energy and a plurality of current loads. Each load may be of a different amount. For each current load, a resistance may be in series between the source and the current load. The resistance may be weighted inversely proportional to the amount of the current load with respect to the other resistances. For each resistance, an integrator may generate an integrated output representative of an integration of the current traveling through the resistance. A summer may generate a summed output which is representative of the sum of each of the integrated outputs, weighted inversely proportional to the resistance that is associated with the integrated output.

Abstract: A method of and system for controlling the inrush current generated in a MOSFET of an inrush current control system, wherein the MOSFET includes a source, gate and drain. The dV/dt at the drain of the MOSFET is controlled so as to set the inrush current level as a function of dV/dt, independent of current limit without requiring a separate capacitor connected between the gate and drain of the MOSFET so that the MOSFET can turn on and off more quickly.

Abstract: Method and system for serially sending data signals captured from multiple sources through a single unidirectional isolation component. Data signals from respective multiple sources are captured in parallel. Such captured data signals are stored in respective storages. The stored data signals are transferred, in serial, from the storages to a single unidirectional isolation component. Multiple concurrent processes for parallel data signal capture and serial data signal transfer via a single unidirectional isolation component are implemented so that the sampling effect on a first of the multiple processes is minimized.

Abstract: A semiconductor device is disclosed that has a die and a substrate having a die attachment area with a perimeter. A layer of solder connects the substrate and the die, the solder layer having at least one vent channel connected to the perimeter of the die attachment area, wherein the maximum distance from any point in the solder layer to the nearest free surface of the solder at a vent channel or at the perimeter of the die is less than the distance from the center of the die to the nearest edge of the die.

Abstract: A clamping circuit clamps a voltage received by an n-type semiconductor region without using a Schottky transistor. The clamping circuit includes a current mirror as well as first and second bipolar transistors. The current mirror receives a first current and supplies a second current in response. The first current is received by the first bipolar transistor, and the second current is received by the second bipolar transistor. The difference between the base-emitter junction voltages of the first and second bipolar transistors, in part, defines the voltage at which the n-type region is clamped. To start-up the circuit properly, current is withdrawn from the base/gate terminals of the transistors disposed in the current mirror. The circuit optionally includes a pair of cross-coupled transistors to reduce the output impedance and improve the power supply rejection ratio.

Abstract: A dynamically-compensated controller may generate a switching signal for a DC power supply. The controller may include a feedback circuit having a first analog-to-digital converter and a separate analyzer circuit for generating information indicative of performance characteristics of the feedback circuit based on information about the results of a test perturbation signal at an output of the DC power supply. The analyzer circuit may include a DC removal circuit configured to substantially filter out the DC component of the results of the test perturbation signal at the output of the DC power supply, a frequency translation circuit configured to translate the frequency of the filtered signal to a frequency that is lower than the frequency of the test perturbation signal, and a second analog-to-digital converter different from the first analog-to-digital converter that is configured to generate a signal representative of one or more of the characteristics of the filtered signal.

Abstract: An over-voltage protection circuit for use in low power integrated circuits is provided. The over-voltage protection circuit distributes certain connection and conditioning circuitry to a component network external to the integrated circuit. As a result, the integrated circuit need not be created with specialized high voltage components, significantly reducing its cost and complexity, and allowing it to be used in a wider range of end-user applications.