Abstract: A power measurement circuit and method are described. The circuit comprises: a transconductance rectifier arrangement including an input and configured to receive a periodically varying input voltage signal having an approximate 50% duty cycle; and an averaging filter for producing a time averaged DC output signal proportional to the mean square of the voltage at the input of the transconductance rectifier arrangement and representative of the average power of the input voltage signal within a range of voltages at the input.

Abstract: An error amplifier may be part of a voltage regulator and may include a single feedback input configured to receive a feedback signal. A single error output may be configured to provide an error output signal indicative of error in the feedback signal. A comparison circuit may be configured to provide an error signal to the single error output which is indicative of a difference between the feedback signal and whichever one of a set of reference signals is closest to the feedback signal. One or more of these reference signals may each be derived from an offset from a ground reference. One or more of the other reference signals may each be derived from an offset from a non-ground reference, such as a source of power for the error amplifier. The error amplifier may be on a single integrated circuit along with an associated driver circuit.

Abstract: A pulse generator circuit in a DC-to-DC converter may be configured to generate pulses that have a frequency that increases in response to increases in the load on the DC-to-DC converter. The pulse generator circuit may be configured to cause each pulse to have a constant width. When the pulse reaches the end of the constant width and the magnitude of the current through an inductance in the converter is less than a threshold value, however, the pulse generator may be configured to extend the pulse until the magnitude of the current through the inductance reaches the threshold value. The pulse generator circuit may be configured to prematurely terminate each pulse if and at such time as the load voltage exceeds a target value by approximately half of the peak-to-peak voltage of the ripple component plus the noise component margin.

Abstract: A switching circuit approximating the fast switching characteristics and small forward voltage drop of an ideal diode is provided. The switching circuit may include a voltage multiplier circuit, a reservoir capacitor and a pull up switch configured to be coupled to the control terminal of a semiconductor switch.

Abstract: A method of preparing a portion of the side of a terminal of an Integrated Circuit (IC) package for solder is disclosed. The method comprises the steps of attaching an IC die to a leadframe comprising a connecting bar, reducing the thickness of a portion of the connecting bar, overmolding the leadframe with a mold compound, removing the mold compound from the reduced-thickness portion of the connecting bar using a laser, coating the reduced-thickness portion of the connecting bar with a solder-wettable material, and cutting through the thickness of the connecting bar within the reduced thickness portion of the connecting bar, wherein the cut has a width that is less than the width of the reduced thickness portion of the connecting bar.

Abstract: A system is configured and a method is provided for receiving an input ratio represented by a first input signal and a second input signal, and producing an output ratio represented by a first output signal and a second output signal. The system is constructed and the method is provided for alternately operating in at least two time periods, wherein in one time period the first input signal, a low accuracy amplifier, and the first output signal are selectively coupled, and in another time period the input signal, the low accuracy amplifier, a high accuracy attenuator, and the second output signal are selectively coupled so as to maintain the output ratio proportional to the input ratio.

Abstract: A power supply system for providing power to a powered device over a communication link includes a power supply device capable of supporting an AC disconnect-detect function. The power supply device has a controller, an output port coupled to the communication link, and a bipolar junction transistor (BJT) controlled by the controller to provide power to the output port. The BJT may be turned off to present a high impedance required to support the AC disconnect-detection function.

Abstract: A flyback controller may receive a chopped and rectified AC voltage from a dimmer control, each cycle of which may have a controllable off period that is substantially attenuated but not always zero due to leakage of the dimmer control, and a controllable on period that substantially tracks the AC voltage. The flyback controller may include a control circuit configured to generate a switching signal based on the signal from the dimmer input. The switching signal may controllably oscillate between its on and off states during the on periods of the chopped and rectified AC voltage so as to controllably regulate current that is delivered by a secondary winding of a transformer in a flyback converter. The switching signal may be in the on state during the off periods of the chopped and rectified AC voltage, thereby preventing a voltage build up from the dimmer control leakage.

Abstract: A chopper stabilized bandgap voltage reference circuit comprises current mirror circuitry mirroring first and second currents into first and second networks to generate a forward diode voltage signal and a PTAT (proportional to absolute temperature) component signal, and a third current having a derived temperature coefficient into a third network to generate a reference voltage signal for a regulator. An amplifier amplifies a differential signal of the forward diode voltage signal and the PTAT component signal to output a fourth current to control the first and second currents. According to a chopper clock, a modulator modulates the differential signal to be supplied to the amplifier and a demodulator demodulates the fourth current. A gain loop compensation circuit is coupled to the demodulator to compensate the amplifier, and filter the fourth current for noise components, and a bypass circuit is also provided to the third network for filtering the third current.

Abstract: A system is configured and a method is provided for receiving an input ratio represented by a first input signal and a second input signal, and producing an output ratio represented by a first output signal and a second output signal. The system is constructed and the method is provided for alternately operating in at least two time periods, wherein in one time period the first input signal, a low accuracy amplifier, and the first output signal are selectively coupled, and in another time period the input signal, the low accuracy amplifier, a high accuracy attenuator, and the second output signal are selectively coupled so as to maintain the output ratio proportional to the input ratio.

Abstract: Switching regulator circuits and methods are provided for regulating output voltage that include an adjustable minimum peak inductor current level and adjustable burst comparator hysteresis for Burst Mode operation in switching regulators. Control over minimum peak inductor current level and burst comparator hysteresis is achieved during Burst Mode operation by allowing external user control of the burst threshold level and the burst comparator hysteresis. A single user-accessible input pin, two user-accessible input pins, or three user-accessible input pins may be used to distinguish between forced continuous and Burst Mode operations, set a burst threshold level, and set a burst comparator hysteresis during Burst Mode operation. The present invention may be applied to buck, boost, buck-boost, or any other suitable regulator circuit configuration. The present invention also may be employed with synchronous and non-synchronous switching regulators.

Abstract: An efficiency measuring circuit may measure the efficiency of a DC-DC converter having a switching inductor with an internal DC resistance and a plurality of electronic switches that control current through the inductor. A duty cycle circuit may measure the duty cycle of current flowing through one of the electronic switches. A current sense circuit may measure the current flowing through one of the electronic switches. An inductor voltage sensor circuit may measure the voltage across the inductor. A computation circuit may compute the internal DC resistance of the switching inductor based in part on the duty cycle measured by the duty cycle circuit and the current measured by the current sense circuit. The computation circuit may also compute the efficiency of the DC-DC converter.

Abstract: System and method for a clock driver. An input taking circuit is used for receiving small-signal logic inputs. A voltage follower circuit is coupled to the input taking circuit and used to generate a set of voltage follower outputs. An output circuit is coupled to the voltage follower circuit to receive the set of voltage follower outputs as inputs and generate output signals. The voltage follower circuit is coupled to a switching circuit, that is connected to the set of voltage follower outputs and is deployed for reducing the phase noise level of the output signals.

Abstract: A valley current mode DC-to-DC converter may include an electronic control system configured to cause the DC-to-DC converter to operate under a continuous current mode and a discontinuous current mode. The electronic control system may include a current sensing system configured to sense current traveling through an inductance, a dual threshold generator configured to generate a first and a different second threshold, and a comparator system configured to compare current sensed by the current sensing system with the first threshold when the DC-to-DC converter is operating in the continuous current mode and with the second threshold when the DC-to-DC converter is operating in the discontinuous current mode.

Abstract: A buck-boost converter with a switch controller may cause switches A, B, C, and/or D to cyclically close such that switches B and C are closed during at least one interval of each cycle during both the buck and boost modes of operation. The switch controller may in addition or instead cause switches A, B, C, and/or D to cyclically close based on a control signal such that switches A and D are closed during an interval of each cycle and such that these intervals are never both simultaneously modulated by a small change in the control signal during any mode of operation.

Abstract: In one embodiment, an A/D converter samples an analog input signal voltage by applying the input signal to a first capacitor terminal, while a second capacitor terminal is connected to ground via an NMOS sampling switch, to charge the capacitor to the input signal voltage. During an analog-to-digital conversion process, the second capacitor terminal may swing in a voltage range that extends below ground. A controller circuit provides bias voltage signals to a gate terminal and to a p-well of the NMOS sampling switch, to selectively turn the sampling switch on and off. In a first step of a multi-step sampling process, the controller very quickly discharges the gate terminal to ground to isolate a quantity of charge on the second capacitor plate. In a subsequent step of the sampling process, the controller circuit applies a negative voltage to the gate terminal and p-well to ensure that the quantity of change is substantially preserved during the ensuing analog-to-digital conversion process.

Abstract: A semiconductor device such as a field-effect transistor, improved to reduce device resistance, comprises a leadframe which includes a die paddle integral with a first set of leads and a second set of leads that is electrically isolated from the first set, a semiconductor die having its lower surface positioned on, and electrically connected to, the die paddle, and a conductive layer on the upper surface of the die. At least one electrically conductive wire, preferably plural wires, extend laterally across the second surface of the semiconductor die, are in electrical contact with the conductive layer, and interconnect corresponding second leads on opposite sides of the die. The plural wires may be welded to leads in succession by alternate ball and wedge bonds on each lead. The conductive layer may be an aluminized layer on which is formed a thin layer a solderable material, such as tin. A solder is deposited on the tin layer, enmeshing the wires.

Abstract: Methods and apparatus for sampling an input voltage and apparatus incorporating the same are disclosed. An input voltage sampling apparatus includes a voltage sampling circuit coupled to the input voltage and configured to produce a sampled input voltage at an output terminal, and a voltage charging circuit coupled to the voltage sampling device and producing a first charged voltage on a first charged voltage output terminal and a second charged voltage on a second charged voltage output terminal. A voltage charging enabling circuit is coupled to the voltage charging circuit, the voltage sampling device via the first connection, and a power supply voltage. Further, the input voltage sampling apparatus includes a control circuit coupled to the voltage sampling circuit, the voltage charging circuit, and the power supply voltage, ground, third and fourth pulse signals. The first and third pulse signals are non-overlapping with the second and fourth pulse signals.

Abstract: An automatic voltage compensation circuit in a voltage regulator compensates the output voltage for a voltage drop along lines leading to a remote load. A load capacitor is connected across the load for providing a low impedance across the load during a test phase of the regulator. In one embodiment, during the test phase, the load current is changed up or down a small percentage (e.g., 10%). As a result, the regulator voltage changes due only to the line resistance since the load is bypassed by the load capacitor. The voltage drop at full load current is then derived by detecting the change in regulator output voltage (a fractional voltage drop) and multiplying it. The normal mode is resumed, and the derived voltage drop is added to the regulator output by either compensating the feedback loop or by adding the voltage drop to the output of the regulator.

Abstract: A device for forming structurally stable curved structures includes an elongated element (10) with a number of segments (12) interconnected at effective hinges (14) to allow deflection of each segment relative to adjacent segments between a reduced-curvature state and a flexed state. Neighboring segments have interlocking features (16) forming an inter-segment locking configuration such that, when the segments are deflected from the reduced-curvature state to the flexed state, the interlocking features interlock adjacent of the segments so as to retain the segments in the flexed state corresponding to a predefined curved configuration of the elongated element. Additionally, or alternatively, a leading portion (44) and a rear portion (40) of the elongated element have features forming at least part of a loop-lock configuration effective to lock together the leading portion and the rear portion so as to form a closed loop structure.