Abstract: In an A/D converter, isolation switches are used between the capacitors and the conversion switches. The conversion switches are those switches used to selectively couple the plates of the binary weighted capacitors to either Vref or 0 volts during the A/D conversion process. During sampling of the input voltage signal, the isolation switches are opened to isolate the conversion switches from the wide range of possible input voltages at the bottom plates of the capacitors. Therefore, the voltage across the conversion switches is substantially limited to Vref. Hence, the conversion switches can be very fast low voltage switches. After sampling of the input voltage, when the sampled input voltage is locked in, the conversion switches operate normally to selectively connect the capacitor plates to either Vref or 0 volts for successively approximating the input voltage, whereby a digital code representing the sampled input voltage is generated.

Abstract: An average current mode switching converter is described for providing a regulated output current independent of load conditions, and a regulated output voltage as a function of the load connected to the converter. The converter includes an inductor, a modulator, a feedback loop, and a precharger. The modulator is configured to provide a regulated current through the inductor The feed back loop is coupled between the inductor and the modulator for regulating the current through the inductor. The precharger is configured and arranged so as to provide and maintain a preset minimum current through the inductor independent of the load so as to improve the recovery time of the converter from a step in the desired regulated output current. Also disclosed is a method of providing a regulated output current independent of load conditions at the output of an average current mode switching converter, and a regulated output voltage as a function of the load connected to the output of converter.

Abstract: An oscillator that includes an energy storage system configured to store energy, a ramp circuit configured to generate an oscillating ramp signal having a slope that is a function of the amount of energy stored in the energy storage system, a charge circuit configured to controllably deliver energy into or remove energy from the energy storage system, a comparator circuit configured to compare the oscillating ramp signal with a reference signal; and/or a charge control circuit configured to cause the charge circuit to deliver energy into or remove energy from the energy storage system based on the comparison by the comparator circuit.

Abstract: Protection circuitry protects a boost converter coupled between input and output nodes for driving a load coupled to the output node. The protection circuitry may comprise a first circuit configured for monitoring a voltage at the output node, the voltage being caused by a signal having a voltage proximate to, or lower than, an input voltage of the boost converter. The protection circuitry may also include a second circuit configured for coupling together the input node with respect to the output node and enabling the boost converter only if the monitored voltage exceeds a reference voltage.

Abstract: In an A/D converter, isolation switches are used between the capacitors and the conversion switches. The conversion switches are those switches used to selectively couple the plates of the binary weighted capacitors to either Vref or 0 volts during the A/D conversion process. During sampling of the input voltage signal, the isolation switches are opened to isolate the conversion switches from the wide range of possible input voltages at the bottom plates of the capacitors. Therefore, the voltage across the conversion switches is substantially limited to Vref. Hence, the conversion switches can be very fast low voltage switches. After sampling of the input voltage, when the sampled input voltage is locked in, the conversion switches operate normally to selectively connect the capacitor plates to either Vref or 0 volts for successively approximating the input voltage, whereby a digital code representing the sampled input voltage is generated.

Abstract: A synchronous boost DC/DC conversion system comprises an input for receiving a DC input voltage, an output for producing a DC output voltage, a power switch controllable to adjust an output signal of the conversion system, and an inductor coupled to the input. A synchronous rectifier is configurable to create a conduction path between the inductor and the output to provide the inductor discharge. A control circuit is provided for controlling the synchronous rectifier as the input voltage approaches the output voltage, so as to adjust average impedance of the conduction path over a discharge period of the inductor.

Abstract: In the preferred embodiment, a current source is switchable between two precisely defined output currents. A terminal of a coupling capacitor is coupled to the gate of an output MOSFET. The other terminal of the capacitor is switched between two reference voltages to toggle the MOSFET to output the selected one of the two currents. A switchable bias voltage source is coupled to the gate only during the on state of the MOSFET to set the gate voltage of the MOSFET. The current output of the current source is quickly and accurately changed. A reference MOSFET is not directly coupled to the output MOSFET, so there are no slow settling components coupled to the gate of the output MOSFET.

Abstract: A clamping circuit clamps a voltage received by an n-type semiconductor region without using a Schottky transistor. The clamping circuit includes a current mirror as well as first and second bipolar transistors. The current mirror receives a first current and supplies a second current in response. The first current is received by the first bipolar transistor, and the second current is received by the second bipolar transistor. The difference between the base-emitter junction voltages of the first and second bipolar transistors, in part, defines the voltage at which the n-type region is clamped. To start-up the circuit properly, current is withdrawn from the base/gate terminals of the transistors disposed in the current mirror. The circuit optionally includes a pair of cross-coupled transistors to reduce the output impedance and improve the power supply rejection ratio.

Abstract: A current sensor is disclosed. The current sensor includes a leadframe having a die paddle, a portion of the die paddle being configured as a resistive element through which current can flow, and an integrated circuit (IC) die attached and thermally coupled to the die paddle. The IC die includes a current sensing module configured to measure a voltage drop across the resistive element and convert the voltage drop measurement to a current measurement signal and a temperature compensation module electrically coupled to the current sensing module. The temperature compensation module is configured to adjust the current measurement signal to compensate for temperature-dependent changes in the resistive element. The temperature compensation module includes a temperature-sensitive element, with a portion of the temperature-sensitive element located directly over a portion of the resistive element.

Abstract: A flyback controller may generate a switching signal for controlling the delivery of input current into a primary winding of a transformer in a flyback converter that has a secondary winding in the transformer and that is driven by AC output from a dimmer control that is chopped at a phase angle based on a setting of the dimmer control. The flyback controller may include a tracking input configured to receive a dimmer output tracking signal that is representative of the instantaneous magnitude of the output from the dimmer control. The flyback controller may include an averaging circuit configured to average the dimmer output tracking signal so as to generate an average dimmer output signal that is representative of a time-averaged value of the dimmer output tracking signal. The flyback controller may be configured to cause the average output current in the secondary winding of the transformer to vary as a function of the average dimmer output signal when the phase angle exceeds a threshold.

Abstract: Circuits and methods that improve the performance of reference circuits are provided. A reference generator circuit maintains a substantially constant output current over an extended temperature for use as a reference. Output current fluctuations caused by a poorly specified power source or process variations are minimized or eliminated.

Abstract: A packaging technique is described for QFNs, DFN, and other surface mount packages that allows the sides of leads to be plated with a wettable metal prior to the lead frames being singulated from the lead frame sheet. The leads of the lead frames in the sheet are shorted together and to the body of the lead frame sheet by a sacrificial interconnect structure. Chips are mounted to the lead frames and encapsulated, leaving the bottoms of the leads exposed. The lead frame sheet is then sawed along boundaries of the lead frames but not sawed through the interconnect structure. The sawing exposes at least a portion of the sides of the leads. The leads are then electroplated while the leads are biased with a bias voltage via the interconnect structure. After the plating, the lead frame sheet is sawed completely thorough the interconnect structure to singulate the lead frames and prevent the interconnect structure from shorting the leads together.

Abstract: A circuit for providing electrical isolation of Power Sourcing Equipment (PSE) circuitry from external circuitry in a Power over Ethernet (PoE) system has an inductive circuit for providing an isolation barrier to electrically isolate an isolated side of the isolation circuit from a non-isolated side of the isolation circuit. A signal path circuitry is configured for transferring bidirectional and/or unidirectional signals over the isolation barrier between respective nodes at the isolated and non-isolated sides.

Abstract: A current sense resistor circuit may include a primary current sense resistor that drifts with age. A secondary current sense resistor may drift with age in substantial unison with the primary current sense resistor. A calibration resistor may not drift with age in substantial unison with the primary current sense resistor. A compensation circuit may compensate for aging drift in the resistance of the primary current sense resistor based on a comparison of the calibration resistor with the secondary current sense resistor. The secondary current sense resistor may be in parallel with the primary current sense resistor, except when the compensation circuit is comparing the calibration resistor with the secondary current sense resistor.

Abstract: A DC/DC converter may include a power stage circuit, a pulse generator circuit, a flux density monitor, and power control logic. The power stage circuit includes an input, an output, and a transformer with a core. The power stage circuit may be configured to operate in a power transfer mode during which power is transferred from the input to the output and a reset mode during which flux density in the core of the transformer is reduced. The pulse generator circuit may be configured to generate pulses that regulate the output of the power stage circuit. The flux density monitor circuit may be configured to generate flux density information indicative of the flux density of the core of the transformer during both the power transfer mode and the reset mode. The power stage control logic may be configured to regulate the output of the power stage circuit based on the pulses and to prevent the core of the transformer from saturating based on the flux density information.

Abstract: An embodiment of an analog-to-digital converter system is described wherein an analog voltage signal Vin(t) is provided by an input amplifier. The analog signal Vin(t) has a predetermined full-scale range that is less wide than a reference voltage (Vref) range used by a downstream ADC to derive a first digital (numerical) representation D1(k) of a sampled value Vin(k) of the analog signal Vin(t). The first digital representation has N bits. A digital circuit then converts the N-bit D1(k) code to a second numerical representation D2(k) of the sampled analog voltage Vin(k) with respect to the full-scale range of the ADC system. The D2(k) code has P bits of resolution, which may be less than N bits. The P-bit D2(k) code representing Vin(k) is the output of the ADC system. Therefore, the width of the reference voltage range applied to the ADC is greater than the width of the system's full-scale range at the output of the system.

Abstract: A synchronous boost DC/DC conversion system comprises an input for receiving a DC input voltage, an output for producing a DC output voltage, a power switch controllable to adjust an output signal of the conversion system, and an inductor coupled to the input. A synchronous rectifier is configurable to create a conduction path between the inductor and the output to provide the inductor discharge. A control circuit is provided for controlling the synchronous rectifier as the input voltage approaches the output voltage, so as to adjust average impedance of the conduction path over a discharge period of the inductor.

Abstract: An apparatus for an improved operational amplifier. The disclosed improved operational amplifier comprises an operational amplifier, a first feedback circuit, and one or more secondary feedback circuits. The operational amplifier include a plurality of serially coupled gain stages and is configured so that an output of each gain stage drives an input of a next gain stage and an output of a last gain stage drives a load external to the improved operational amplifier. The first feedback circuit is coupled between an output of a designated gain stage and an output of a previous gain stage to provide a first feedback to the previous gain stage. Each secondary feedback circuit provides an additional feedback to the output of the previous gain stage.

Abstract: System and method for a light emitting diode (LED) driver are disclosed. To supply an LED bus voltage to a large array of LEDs organized in multiple channels where one or more LEDs are connected in series in each channel, an LED driver includes a power converter, a feedback generation circuit, and a phase-division based controller. The power converter is configured for providing the LED bus voltage to the multiple LED channels based on a voltage control signal. The feedback generation circuit is configured for generating a feedback signal based on the LED bus voltage supplied to the multiple LED channels. The phase-division based controller is configured for generating the voltage control signal based on the feedback signal and information from the multiple LED channels.

Abstract: An LED driver circuit that includes a buck-mode boost converter that provides a regulated output current and that requires only a single connection to each channel of LEDs. The buck-mode boost controller may include a current regulator that includes an integrator. The current regulator may be configured to integrate a difference between a reference signal that is representative of the desired level of the average current through the electronic power switch and a detected signal that is representative of the actual current that is being delivered to the buck-mode boost circuit through the electronic power switch. The reference signal to the integrator may not change during operation of the buck-mode converter. The current regulator may be configured to deactivate the integrator and/or to disconnect the detected signal from the integrator while the electronic power switch is off.