Abstract: A variable gain amplifier contains a plurality of differential transistor pairs. A temperature dependent current is generated in the current path of each differential transistor pair. A generated gain control current is converted to a temperature dependent gain control current and applied in circuit with control inputs of the transistors of the paired differential transistors. The temperature dependent gain control current is obtained from a gain control current corresponding to a desired gain which is then multiplying the control current by the temperature dependent current. The temperature dependent gain control current is modified to compensate for gain non-linearity by introducing an offset as a function of the gain control current.

Abstract: A plurality of variable gain amplifier stages are coupled by an attenuation circuit that receives a voltage input to be amplified. A control circuit activates each of the variable gain amplifier stages in a seamless manner in accordance with a control signal applied to a voltage control node, while maintaining no more than one of the stages active at any time. Fractions of the reference signal voltage level are set to define boundaries between control voltage level ranges of the amplifier stages. A unique control voltage level range is thus established for each amplifier stage. A control voltage hysteresis range can be provided to avoid oscillations between stages at the transition voltages.

Abstract: Circuitry and methods for improved amplifiers with large bandwidth and constant gain are provided. The combination of a synthetic inductive drain load and a bridged-T matching network provide amplifiers that can drive a substantial capacitive load with the above mentioned improvements over prior amplifiers. Additionally, circuits presented allow for improved rise time and insensitivity to temperature variations.

Abstract: A switched regulator circuit provides step-up and step-down operation at high efficiency during light load conditions. Switching loss is reduced in a four switch arrangement by limiting bottom MOSFET switching frequency. The possibility of overcharge in boost mode operation has been avoided by automatically changing to a buck mode operation in response to sensed parameters.

Abstract: A network comprises an arrangement of regular structures and merged structures, in which the regular structures each comprise one or more mutually identical fixed elements and an equal number of adjustable elements of equal value, and the adjustable elements each comprising two or more adjustable units. The regular structures may comprise one or more mutually identical fixed elements and an equal number of adjustable elements of equal value. The adjustable elements each comprise two or more adjustable units, and the merged structures comprise N mutually identical fixed elements and one merged adjustable element. The merged adjustable elements have substantially the same value as that of N adjustable elements, where N is an integer equal to or greater than 2, and the merged elements each may comprise one or more adjustable units. The network accordingly is trimmable in a manner that uses minimum area and consumes minimum time during manufacture.

Abstract: Circuitry and methods for obtaining accurate measurements of current supplied by an integrated circuit are provided. Current calculations are performed using information from a precision termination resistor and from the ratio relationship of two on-chip resistors. The invention provides a way to obtain accurate current measurements without the use of component trimming.

Abstract: Variable gain amplifiers offering high frequency response with improved linearity and reduced power dissipation are provided. An amplifier is disclosed that is constructed from a one-stage topology with multiple signal paths and compensation networks for improved linearity and stable operation. In this amplifier, improved performance is obtained by replacing single transistor components with enhanced active devices which incorporate local negative feedback. One embodiment of the invention is a transconductance enhancement circuit that improves transconductance and input impedance relative to the prior art. A further development is an enhanced active cascode circuit that provides improved linearity. A high frequency bipolar transistor switch is also disclosed that incorporates lateral PNP transistors as high frequency switches with improved OFF-state to ON-state impedance ratio to realize a variable gain function.

Abstract: Electronic devices, and methods, for transmitting, transferring and/or conveying a multi-bit digital signal as a voltage signal via a single pin. Devices and methods according to the invention substantially reduce the pin count of a device because inputting of a multi-bit digital signal preferably does not use more than one input pin. In addition, the speed of transmission is improved because the multi-bit digital signal is transmitted as a voltage signal substantially at one time as opposed to serially.

Abstract: Novel system and methodology for distinguishing a Network Interface Card (NIC) from a short circuit condition in a Power over Ethernet (PoE) system. A system for providing power to a powered device (PD) includes a PD probing circuit that generates a detection signal supplied to a device being probed and determines a response signal produced in response to the detection signal, and a control circuit that determines a detection value based on the response signal. The control circuit detects a short circuit if the detection value is in a first predetermined range, and detects a NIC if the detection value is in a second predetermined range outside of the first predetermined range.

Abstract: System for controlling the frequency of an oscillator. A first circuit is coupled to the oscillator and arranged for receiving an externally provided clock signal at a first input node. A second circuit coupled to the oscillator is arranged for receiving an externally provided frequency reference input at a second input node. The first circuit uses the clock signal received at the first input node to control the frequency of the oscillator. In absence of a clock signal received at the first node, the second circuit uses the frequency reference input received at the second input node to control the frequency of the oscillator. The frequency reference input is selectively at one of (a) a first or second fixed voltage level designating a first or second oscillator frequency, and (b) a variable signal level designating a frequency between the first and second oscillator frequencies.

Abstract: A method and circuit for driving the gate of a MOS transistor having a negative or low threshold voltage negative, in which the driving circuit is formed on a single chip. A negative voltage is generated from a positive voltage to drive the gate of the MOS transistor negative. The MOS transistor may be a native NMOS transistor, and the negative voltage is generated for increasing source-drain impedance of the native NMOS transistor. On the other hand, the MOS transistor may be a PMOS transistor, and the negative voltage is generated for reducing source-drain impedance of the PMOS transistor. The MOS transistor can be used as an open-drain switch or a source follower.

Abstract: Voltage offset of an integrated circuit amplifier is accurately determined for calibration of the device. Circuit connections are established between the integrated circuit and an external device, such as an IC handler. Internal noise gain resistors formed within the integrated circuit are connected by internal switches to the amplifier and the output voltage is measured so that a value of a voltage offset of the amplifier while the noise gain resistors are connected can be calculated. The use of internal noise gain resistors produces a voltage offset component of the output voltage that is significantly greater in magnitude than effects of thermocouple voltages generated by circuit junction connections.

Abstract: A disclosed amplifier and buffer circuit, for example for a linear voltage regulator, comprises an input gain stage, an integrator and a unity-gain output stage. An output stage compensation scheme enables stable operation over a broad range of output capacitance. For low to moderate output capacitance, the design of the output stage effectively pushes the output pole to high frequencies while an internal pole provided by the integrator is dominant and rolls off the gain at lower frequencies. For high output capacitance, an input impedance of the buffer couples the internal pole and output pole, such that the output pole becomes dominant while the internal pole gets pushed to higher frequencies, maintaining stability. This input impedance connection may utilize the base-emitter resistance of a bipolar junction transistor connected to the internal node, or the connection may use an MOS transistor and a separate RC circuit.

Abstract: An amplifier includes differential current sensing circuitry and an input bridge. Two paths of the input bridge receive the input signals and provide proportional current flows to the differential current sensing circuitry. The input bridge is configured to provide a differential offset voltage in one current path, and a complimentary voltage drop of equal magnitude in the other current path. In the examples, the input bridge includes a matched pair of transistors. To remove parallel incremental or small-signal conductance-related error sources, both transistors are operated at matched VDS (drain-to-source) voltages. The voltage offset, provided in association with one of the input transistors, serves to extend the range of certain circuits using the amplifier. The complimentary voltage drop in association with the other input transistor maintains the match of the VDS voltages for the two transistors.

Abstract: A method of and system for regulating voltage supplied by a local power supply to a remote load includes sensing a low frequency portion of the output voltage at the remote load, locally sensing a high frequency portion of the output voltage produced by the local power supply, and in response, controlling the output of the supply.

Abstract: A CMOS driver with minimum shoot-through current is disclosed. The potential for shoot-through current may be eliminated or reduced with a break-before-make circuit driving an output stage. The break-before-make circuit may include a first logic element followed by a first inverter and a second logic element followed by a second inverter. The inverters may be cross-coupled to one another and/or the internal transistors may be configured with different strengths. The logic elements may be configured to eliminate or reduce potential shoot-through current paths, and the signal inputs may be controlled within a certain voltage range.

Abstract: Circuitry and methods for improved amplifiers with large bandwidth and constant gain are provided. The combination of a synthetic inductive drain load and a bridged-T matching network provide amplifiers that can drive a substantial capacitive load with the above mentioned improvements over prior amplifiers. Additionally, circuits presented allow for improved rise time and insensitivity to temperature variations.

Abstract: A signal processing methodology and circuit for supplying bias power and duty cycle information across an isolation barrier, wherein, at an input side of the isolation barrier at least one input signal carrying input duty cycle information, together with DC bias power, is received and encoded on a constant repetition rate, constant duty cycle carrier waveform. Encoding is carried out by an encoder implemented to encode the carrier waveform with a marker, such as a waveform discontinuity, at a timing corresponding to the input duty cycle information, and wherein the presence of the marker leaves the average value of the carrier waveform unaffected. At the output side of the isolation barrier, the duty cycle information may be received by a decoder, the input duty cycle information detected to reconstruct the at least one input signal, and optionally DC bias power extracted from the carrier waveform.

Abstract: Pulse width modulation of the connection of a load output terminal to a power supply terminal is effected. In response to a first level of the pulse width modulated signal, the load is disconnected from the power supply terminal, steady-state load voltage is preserved on a capacitor connected between a load output terminal and a power supply terminal, and steady-state load current information is held on a capacitor within the feedback loop. In response to a second level of the pulse width modulated signal, the load is reconnected to the power supply terminal, and load voltage and current instantaneously resume at their correct steady-state values.

Abstract: Circuits and methods to correct the load sharing in multiphase switching regulators are provided. Using these systems and methods, the input capacitor voltage signal can be sampled and used for current sensing of the regulator's stages. Differences in the amount of output current for a converter stage can then be determined. Corrections needed to equalize the output current of the converter stages can then be determined and carried out.