Abstract: Compensation for a switching regulator is attained by developing a compensation signal for a switching regulator that is independent of changes in the switching frequency. The regulator operational frequency is established in accordance with a repetitive ramp signal of constant slope and adjustable frequency. The voltage of the ramp signal is monitored and an offset signal is derived therefrom. The peak value of the ramp signal, detected during monitoring, is used to derive the offset signal. Initiation of the compensation occurs at the same duty cycle point during each switching cycle and thus is independent of switching frequency. The compensation signal may have a linear or non-linear slope.

Abstract: A circuit for charging a photoflash that preferably reduces the average input to the switching regulator in an efficient fashion is provided. The regulator includes a transformer. The transformer includes a primary winding and a secondary winding. The switching regulator also includes a switch that closes at the beginning of a first portion of the switching cycle and opens at the end of the first portion of the switching cycle. The second portion of the cycle may be to allow the secondary winding to release current into the load. The switch is adapted to allow the current to build up in the primary winding when the switch is closed. The switching regulator may also include a delay circuit that introduces a delay between the end of the second portion of the cycle and the beginning of the first portion of the next switching cycle.

Abstract: The present invention relates to methods and circuits for controlling outputs of one or more slave power supplies in one or more defined relationships to a master signal. The defined relationships include but are not limited to coincident tracking, offset tracking, ratiometric tracking, and supply sequencing.

Abstract: Circuitry and methods for improved amplifiers with large bandwidth and constant gain are provided. The combination of a synthetic inductive drain load and a bridged-T matching network provide amplifiers that can drive a substantial capacitive load with the above mentioned improvements over prior amplifiers. Additionally, circuits presented allow for improved rise time and insensitivity to temperature variations.

Abstract: Circuitry and methodology for controlling a FET or another transistor device provided to supply power to a circuit board insertable into a live backplane to provide inrush current slew rate control. The FET control circuit is responsive to an input signal variable in a preset manner to produce a FET control signal for controlling the FET so as to form an output signal corresponding to the input signal. The control circuit is configured to prevent the uncontrollable step in the output from being produced when the FET control signal reaches a level sufficient to control the FET. In one embodiment, a comparator is provided for comparing the FET control signal with a reference value that may correspond to a current for charging a control terminal of the FET to prevent the input signal from changing until the FET control signal exceeds the reference value.

Abstract: Switching regulator circuits and methods are provided for regulating output voltage that include an adjustable minimum peak inductor current level and adjustable burst comparator hysteresis for Burst Mode operation in switching regulators. Control over minimum peak inductor current level and burst comparator hysteresis is achieved during Burst Mode operation by allowing external user control of the burst threshold level and the burst comparator hysteresis. A single user-accessible input pin, two user-accessible input pins, or three user-accessible input pins may be used to distinguish between forced continuous and Burst Mode operations, set a burst threshold level, and set a burst comparator hysteresis during Burst Mode operation. The present invention may be applied to buck, boost, buck-boost, or any other suitable regulator circuit configuration. The present invention also may be employed with synchronous and non-synchronous switching regulators.

Abstract: An integrated circuit providing high equivalent capacitance ranging from a few tens of picofarads to a few nanofarads is presented. The integrated circuit includes active integrated circuit components, requires no external capacitor, and is substantially insensitive to transistor current gain variations. The high capacitance integrated circuit can be advantageously used to provide, for example, timing delay and servo loop compensation.

Abstract: Circuitry and methodology for providing LED dimming control in a LED driving system having a switching regulator for providing power supply to drive the LED. The switching regulator includes a switching circuit to which an oscillation signal is applied to control switching of the switching circuit. A dimming control input is supplied with a pulse-width modulation (PWM) dimming control signal to provide PWM dimming control of the LED. The dimming control input applies the PWM dimming control signal to control switching of the switching circuit. A synchronizing circuit is provided for synchronizing the oscillation signal to the PWM dimming control signal.

Abstract: An analog-to-digital converter according to the invention is provided. The analog-to-digital converter preferably includes an analog input signal, a first reference signal, a second reference signal, and a range compression signal. The range compression signal is preferably characterized by a magnitude greater than the first reference signal and smaller than the second reference signal. In addition, when the analog input signal is sampled N times and the range compression signal is sampled N1 times, a compression factor that is based at least in part on N1/(N+N1) is obtained.

Abstract: An analog-to-digital converter according to the invention is provided. The analog-to-digital converter preferably includes an analog input signal, a first reference signal, a second reference signal, and a range compression signal. The range compression signal is preferably characterized by a magnitude greater than the first reference signal and smaller than the second reference signal. In addition, when the analog input signal is sampled N times and the range compression signal is sampled N1 times, a compression factor related at least in part to the ratio N1/(N+N1) is obtained.

Abstract: A variable gain amplifier comprises a plurality of serially connected transistor cells, in which each of the transistor cells has a plurality of connecting terminals. The first terminals of the transistor cells are serially coupled together to receive a first input voltage. The second terminals of the transistor cells are serially connected via a first set of resistors between adjacent cells and coupled to a first gain control. Each of the second terminals is AC or virtual grounded. The third terminals of the transistor cells are coupled together to supply a positive current output. The fourth terminals of the transistor cells are coupled together to supply a negative current output.

Abstract: Light emitting elements with preselected or adjustable impedance characteristics are provided. Embodiments using a preselected impedance characteristic obtain significant performance benefits compared to the prior art. Embodiments having an adjustable impedance may alter the impedance associated with the light emitting component such that it has a substantially constant resistive or reactive impedance that improves certain performance attributes. This solution virtually eliminates the need for external compensation components and relieves the burden of impedance matching and circuit specialization from the driver circuit.

Abstract: A current squaring cell is provided for producing an output current that correlates to the square of an input signal current. The current squaring cell comprises a first circuit portion, which receives a first tail current that is positively proportional to the input signal current, and a second circuit portion, which connects to the first circuit portion and receives a second tail current that is negatively proportional to the input signal current.

Abstract: The present invention provides a capacitor charging circuit that efficiently charges capacitive loads. In particular, circuits and techniques are preferably provided for using current from both the primary and secondary windings of a transformer to control ON-time and OFF-time of a switch. This arrangement preferably yields an adaptable ON-time and adaptable OFF-time switch that is capable of rapidly charging capacitor loads ranging from as low as zero volts to several hundred volts. The output voltage is preferably measured indirectly to prevent unnecessary power consumption. In addition, control circuitry can be provided to conserve power by ceasing the delivery of power to the capacitor load once the desired output voltage is reached. Control circuitry preferably operates an interrogation timer that periodically activates the power delivery cycle to maintain the capacitor output load in a constant state of readiness.

Abstract: A low voltage pull-down circuit for maintaining a node at a logic LOW voltage is provided. When a logic LOW is desired, the circuit provides a low-impedance path from the node to ground. The node may be pulled-up to a logic HIGH voltage, for example, by removing the low-impedance path and allowing a voltage source to reach the node through a resistor or transistor. A low voltage pull-down circuit may be provided in a power supervision circuit for systems that operate with, for example, low power conditions. The open-drain node is utilized as a power-on-reset node that provides a LOW logic signal to a system when the power being supplied to the system is below a predetermined voltage threshold.

Abstract: An adaptive current reversal comparator for synchronous switching regulator comparison circuit for use in a switching regulator is provided. The comparison circuit includes a voltage offset that is used at least in part to compensate for a propagation delay of the comparison circuit. The switching regulator includes an inductor and a synchronous transistor. The comparison circuit also includes a timing circuit that provides a threshold amount of time and an offset adjustment circuit. The offset adjustment circuit preferably decreases the voltage offset of the comparison circuit when a synchronous transistor control signal transitions to an OFF state more than the threshold amount of time prior to the discharge of an inductor. The comparison circuit also increases the voltage offset of the comparison circuit when the synchronous control signal transitions to an OFF state more than the threshold amount of time following the discharge of the inductor.

Abstract: An adaptive current reversal comparator for synchronous switching regulator comparison circuit for use in a switching regulator is provided. The comparison circuit includes a voltage offset that is used at least in part to compensate for a propagation delay of the comparison circuit. The switching regulator includes an inductor and a synchronous transistor. The comparison circuit also includes a timing circuit that provides a threshold amount of time and an offset adjustment circuit. The offset adjustment circuit preferably decreases the voltage offset of the comparison circuit when a synchronous transistor control signal transitions to an OFF state more than the threshold amount of time prior to the discharge of an inductor. The comparison circuit also increases the voltage offset of the comparison circuit when the synchronous control signal transitions to an OFF state more than the threshold amount of time following the discharge of the inductor.

Abstract: A squaring cell comprises a first circuit responsive to an input voltage to produce a corresponding current, and a second circuit, preferably in the form of an absolute modulator circuit, responsive to the current produced by the first circuit and to the input voltage to produce an output current that corresponds to the square of the input voltage. In one embodiment, the first circuit comprises an absolute value voltage-to-current converter; in another, the first circuit comprises a linear voltage-to-current converter. Techniques to improve accurate square law performance of the cell, independent of temperature, and of broad input voltage range and frequency, are presented.

Abstract: A CMOS driver with minimum shoot-through current is disclosed. The potential for shoot-through current may be eliminated or reduced with a break-before-make circuit driving an output stage. The break-before-make circuit may include a first logic element followed by a first inverter and a second logic element followed by a second inverter. The inverters may be cross-coupled to one another and/or the internal transistors may be configured with different strengths. The logic elements may be configured to eliminate or reduce potential shoot-through current paths, and the signal inputs may be controlled within a certain voltage range.

Abstract: Voltage regulators and methods for regulating voltages are disclosed. A switching circuit with an inductor and a plurality of switches may be used to produce a regulated voltage from an unregulated voltage source. A control circuit may be used to monitor the voltages at the input and output of the voltage regulator, and operate the switches in either a buck, boost, or buck-boost mode depending on the relationship between the voltages at the input and output of the voltage regulator.