Abstract: The present invention is directed to methods for optimizing package and silicon co-design of an integrated circuit. A composite bump pattern for an integrated circuit is created based on a first library including at least one bump pattern template. PCB and Die constraints of the integrated circuit are then reviewed. A partial package design for the integrated circuit is generated based on a second library including at least one partial package template. A partial silicon design for said integrated circuit is started. A full package design for the integrated circuit is then completed. A full silicon design for the integrated circuit is completed.

Abstract: A method and system for performing optical proximity correction (OPC) on an integrated circuit (IC) mask design is disclosed. The system and method of the present invention includes identifying a feature in the IC mask design, generating an isofocal contour for the identified feature, wherein the isofocal contour is a continuum of isofocal points corresponding to points on an edge of the identified feature, and utilizing the isofocal contour to estimate an amount of correction needed to produce a resist image significantly identical to the identified feature.

Abstract: Techniques of designing a digital phase lock loop are disclosed. In one embodiment, the digital phase lock loop comprises a synchronization unit producing a producing a plurality of clock signals in accordance with a seed clock signal having a frequency, each of the clock signals having a modified frequency over the frequency of the seed clock signal and a phase shift from each other; a phase-frequency detection unit receiving an input signal and a feedback signal, and sampling the input signal and the feedback signal in accordance with the clock signals to determine differences in phase and frequency between the input signal and the feedback signal; a digital control oscillator receiving the clock signals and producing an output signal in reference to the differences from phase-frequency detection unit, and subsequently, a digitally controlled clock signal is produced.

Abstract: Systems and methods for maintaining cache coherency between a first controller and a redundant peer controller while reducing communication overhead processing involved in the coherency message exchange. Header or meta-data information is accumulated in a buffer in a first controller along with updated cache data (if any) and forwarded to the peer controller. The accumulating information may be double buffered so that a buffer is filling as a previously filled buffer is transmitting to the peer controller. The peer controller processes the received information to update its mirror cache to maintain coherency with the first controller's cache memory with respect to dirty data. The method and systems avoid the need to update cache coherency in response to every flush operation performed within the first controller to thereby improve overall system performance.

Abstract: A method for monitoring polishing process parameters for an integrated circuit structure on a substrate. A first metrology site is constructed on the substrate. The first metrology site represents a design extreme of a high density integrated circuit structure. The first metrology site is formed by placing a relatively small horizontal surface area trench within a relatively large surface area field of a polish stop material. A second metrology site is also constructed on the substrate. The second metrology site represents a design extreme of a low density integrated circuit structure. The second metrology site is formed by placing a relatively large horizontal surface area trench within a relatively small surface area field of a polish stop material. The substrate is covered with a layer of an insulating material, thereby at least filling the trenches.

Abstract: A barrier layer for a semiconductor device is provided. The semiconductor device comprises a dielectric layer, an electrically conductive copper containing layer, and a barrier layer separating the dielectric layer from the copper containing layer. The barrier layer comprises a silicon oxide layer and a dopant, where the dopant is a divalent ion, which dopes the silicon oxide layer adjacent to the copper containing layer. A method of forming a barrier layer is provided. A silicon oxide layer with a surface is provided. The surface of the silicon oxide layer is doped with a divalent ion to form a barrier layer extending to the surface of the silicon oxide layer. An electrically conductive copper containing layer is formed on the surface of the barrier layer, where the barrier layer prevents diffusion of copper into the substrate.

Abstract: A method and system of testing data retention of memory is provided. An embodiment of the method of testing data retention of memory comprises: writing first data to a first memory sub-group during a first time period; writing second data to a second memory sub-group during a second time period subsequent to said first time period; pausing for a predetermined time interval during a third time period subsequent to said second time period; reading a first one of said first and second data during a fourth time period subsequent to said third time period; reading a second one of said first and second data during a fifth time period subsequent to said fourth time period; and comparing said first and second ones of read data to expected results to determine data retention capabilities of said first and second memory sub-groups.

Abstract: An extended protocol provides a serial bus with the capability of effective communications for a multimaster bus. A bus device may enter a master mode and transmit information identifying a designated recipient device on the bus. Either the master mode device or the designated recipient device may send information that identifies the master mode bus device. The master mode device may read from the designated recipient device or may write to the designated recipient device. The designated recipient device may provide an acknowledgement, data, a command, or status information may be sent back. The status information may include version information regarding the hardware, software, and/or firmware of the designated recipient device.

Abstract: The present invention is directed to a method and system for managing the coherency of mirrored storage volumes, including a method and system for restoring coherency in the event of communication disruption between the primary volume and the secondary volume mirroring the data on the primary volume. The system includes a primary and a secondary storage controllers for managing the primary and secondary storage volumes. The storage controllers are capable of performing cyclic redundancy checking scans of their respective storage volumes and comparing the results to determine data from the primary storage volume needed to update the secondary storage volume so that it mirrors the primary storage volume.

Abstract: Intelligent transportable data storage component module for a data processing system and a method for charging a battery for a data storage component in an intelligent transportable data storage component module. The intelligent transportable data storage component module has a data storage component and an intelligent battery backup for providing power to the data storage component. The intelligent battery backup, for example, a battery backup falling within Smart Battery Specifications, has a battery and a battery charger that function as a unit to monitor and charge the battery independent of the host processor and firmware of the data processing system and independent of characteristics of the battery.

Abstract: A circuit generally comprising a debug port and a processor is disclosed. The processor may be configured to (i) bootstrap to a first memory, (ii) disable said debug port while in a first mode of at least three modes, (iii) authenticate said debug port while in a second mode of said modes and (iv) disable said debug port in response to failing said authentication.

Abstract: A method and apparatus are provided for identifying a potential floorplan problem in an integrated circuit layout pattern. The method and apparatus identify a critical timing path in the layout pattern and identify a start point and one or more end points along the timing path. It is then determined whether any of the one or more end points are floor-planned objects. For each end point that is a floor-planned object, the method and apparatus compare a distance between that end point and the start point with a distance threshold to produce a comparison result. A potential floorplan problem can be identified if the distance exceeds the distance threshold.

Abstract: A method for producing yield enhancement data from integrated circuits on a substrate. A database of defects on the substrate is compared to a database of design information for the integrated circuits. The defects on the substrate are associated with classes of design information to produce the yield enhancement data.

Abstract: In an integrated circuit, test signals are routed from test points through a hierarchy of distributed multiplexers to output pads. The multiplexers are distributed locally to various regions that are arranged in a hierarchy of regional levels. Thus, each test signal is routed to the locally distributed multiplexer, and only a portion of the test signals reach the top-level multiplexer.

Abstract: The present invention is directed to a method and system for optimally mapping a general set of resources to a specific integrated circuit design. In an exemplary aspect of the present invention, a method for optimally mapping a general set of resources to a specific integrated circuit design may include the following steps. Sets of transistors are first abstracted into abstracted resources. The abstracted resources may include a transformative resource, a coordinating resource, and a state management resource, and the like. Then, a sea-of-platforms is utilized for unifying a flexible and malleable collection of the abstracted resources in such a way as to optimize the abstracted resources for a specific integrated circuit design. Broken symmetry may be used to optimize the abstracted resources for the specific integrated circuit design. The broken symmetry may be in at least one of a physical 3-dimensional space, a temporal space and a code space.

Abstract: A circuit generally comprising a command buffer and a read buffer is disclosed. The command buffer may be configured to (i) buffer a plurality of read commands received by the circuit, wherein each read command has one of a plurality of port values and one of a plurality of identification values and (ii) transmit a tag signal from the circuit in response to servicing a particular read command of the read commands. The tag signal may have a particular port value of the port values and a particular identification value of the identification values as determined by the particular read command. The read buffer may be configured to transmit a read signal within a plurality of first transfers from the circuit in response to servicing the particular read command.

Abstract: An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a request count in response to a request head pointer and a request tail pointer. The second circuit may be configured to generate a completion count in response a completion head pointer and a completion tail pointer. The third circuit may be configured to prioritize an interrupt in response to the request and completion counts.

Abstract: An apparatus comprising (i) a first circuit configured to generate one or more node signals at one or more internal nodes and (ii) a second circuit configured to present one or more of the node signals and a trigger signal in response to one or more control signals.

Abstract: An iterative process assigns nodes of a new logical tree to positions in a space that was previously assigned to an old logical tree equivalent to the new logical tree. A path in the new tree is identified for an essential node of the new tree. Coordinates of a position in the space are identified for an old tree node that is equivalent to a son of the essential node. Coordinates are iteratively identified for each node in the new tree path using a free space algorithm and based on the nodes of the new tree path and the coordinates identified for the old tree node that is equivalent to the son of the essential node. If all sons of the essential node are leaves of the new tree, the old tree node is a leaf node equivalent to the son. Otherwise, the old tree node is identified in a prior iteration.

Abstract: A method and system for optimizing a netlist change order flow is disclosed, wherein a design layout created by a layout tool using a reference netlist is to be changed by a modified version of the netlist, and wherein both netlists are hierarchical comprising. Aspects of the present invention include comparing the modified netlist with the original netlist outside of the layout tool, and automatically generating at least one change order based on differences found between the two netlists. After the change order is generated, the change order is then applied to the design layout to generate a modified design layout.