Abstract: A method and apparatus for deinterlacing a picture is disclosed. The method generally includes the steps of (A) calculating a plurality of differences among a plurality of current samples from a current field of the picture, the differences being calculated along a plurality of line segments at a plurality of angles proximate a particular position between two field lines from the current filed, (B) generating a first sample at the particular position by vertical filtering the current field in response to the differences indicating that the particular position is a non-edge position in the picture and (C) generating a second sample at the particular position by directional filtering the current field in response to the differences indicating that the particular position is an edge position in the picture.

Abstract: A method and computer program for screening defects in integrated circuit die includes steps of receiving as input measurements of quiescent current for each die in a sample lot of semiconductor die and generating a test matrix from the quiescent current measurements for each die in the sample lot. A de-mixing matrix is computed from independent component analysis that models passing die in the sample lot. A matrix of sources is generated as a product of the test matrix and the de-mixing matrix. The matrix of sources is normalized to zero mean and unit variance. A statistical limit of the passing die in the sample lot is selected from each of the sources in the normalized matrix of sources to determine a maximum and a minimum quiescent current limit for each of the sources. The maximum and the minimum quiescent current limit for each of the sources is generated as output.

Abstract: A method for returning a logical volume which is part of a redundant data storage system to on-line status following a disk failure within the logical volume during the time when another of that volume's disks is unavailable as a result of having its firmware updated, as an example. Data which would otherwise be changed in the logical volume due to host write requests is directed to a logging facility within the data storage system, but outside of the logical volume undergoing upgrade.

Abstract: A device and method of controlling a de-jitter buffer, and specifically the nominal delay thereof. The nominal delay is adjusted based on delay information associated with a network in which the de-jitter buffer is located. The nominal delay is maintained between a minimum and maximum nominal delay, and is adjusted based on the probability that a packet will arrive outside a predetermined delay interval.

Abstract: A computer-implemented method is disclosed for recognizing edges in a digital image having a plurality of pixels with gray-scale values defining features. The method includes recognizing edges of the features by cearting a new image in which pixels in the new image corresponding to pixels in the gray-scale image that have a brightness value meeting a predetermined threshold are assigned a first binary value to represent edge regions, while remaining pixels in the new image are assigned a second value to represent both background and internal areas of the features. Area recognition is then performed to distinguish internal feature areas from background areas. The method further includes detecting edge lines from the edge regions that separate features from background and internal feature areas.

Abstract: A method for performing motion estimation comprising the steps of (a) determining one or more first vectors representative of a displacement of a first block of a first image in a second image and (b) determining one or more second vectors representative of a displacement of the first block in the second image and a first sub-block and second sub-block of the first block based upon the one or more first vectors, a plurality of error scores, and a combination of the plurality of error scores.

Abstract: An input pad for a differential current input to an integrated circuit contains a switchable and tunable input impedance. The input pad also contains ESD protection and common mode rejection while maintaining low capacitance. The common mode rejection comprises two resistors that combine to remove the common mode current from the two input lines, produce a reference current, and drive two output transistors that cancel the common mode current from the outputs.

Abstract: Methods and structures for managing connection requests within a SAS controller operating as a target device. A SAS target device maintains a table of information regarding known SAS initiator devices in the SAS domain. An index value is supplied in transport layer requests and used by each of a plurality of link layer processing elements in the SAS controller to access information in the table. The index value is fewer bits than the complete eight byte SAS address and the logic to manipulate and compare the index value is therefore simpler than that required to directly manipulate a full SAS address. Further, the information table is shared by each of the link layer processing elements to further reduce complexity from replication of circuits and logic in the SAS controller.

Abstract: A carrier substrate includes an access region placed within the interior of the substrate that facilitates backside access to an integrated circuit die without damaging electrical integrity of the carrier substrate, a ring of die connection pads placed around the access region, and an array of package connection pads positioned around the perimeter of the top surface of the carrier substrate. In one embodiment, the perimeter depth of the array of package connections pads is selected to correspond to the number of electrical traces routable between minimally spaced package connection pads. The basic carrier substrate design is used to create an integrated circuit carrier family with each particular circuit carrier configured to receive a range of integrated circuit sizes and I/O counts such that each circuit carrier overlaps in size range with at least one other circuit carrier.

Abstract: A method of processing Voice band Data in a communication path in a telecommunication network. The communication path consists of a plurality of Voice band Data relay gateways, including a first Voice band Data relay gateway, a last Voice band Data relay gateway, and at least one Voice band Data relay gateway between the first and last Voice band Data relay gateways. The method includes steps of detecting the Voice band Data relay gateway, and disabling the at least one Voice band Data relay gateway between the first and last Voice band Data relay gateways, whereby the at least one Voice band Data relay gateway between the first and last Voice band Data relay gateways does not encode and decode the Voice band Data.

Abstract: A user-defined memory design is mapped to memories of a base platform for an IC that contains a plurality of memory sets, each containing a plurality of memories of a predetermined type. An optimal memory set is selected from the plurality of memory sets for the design by selecting a preference rate for each memory set from the plurality of sets based on the design and its connections to portions of the IC, and selectively assigning the design to one of the memory sets based on the preference rate. The design is optimally mapped to a plurality of memories of the selected memory set by defining an index of the position of each customer memory in the selected memory set. The customer memories in the selected memory set are arranged in an order, and successive numbers of memories of the selected memory set are assigned to each customer memory in order.

Abstract: A method for constructing a logic circuit for inversion in finite field GF(2m) is described, where m=nk, and k, n are coprime numbers, using bases in subfields GF(2n) and GF(2k). The method may be applied to error correction codes, including BCH codes, Reed-Solomon codes (which are a subset of BCH codes), turbo codes, and the like.

Abstract: A computer system having a hierarchical bus structure that allows decoupling of a local bus from a global bus thereof. Decoupling of the local bus is achieved through use of an asynchronous system bus adapter which includes a local bus adapter for handling transactions, initiated by a system device coupled to the global bus, that require access to a local device coupled to the local bus and a global bus adapter for handling transactions, initiated by a local device coupled to the local bus, that require access to a system device coupled to the system bus. The local bus adapter is further configured to issue signals which prevent the global bus adapter from handling transactions initiated by local devices coupled to the local bus while transactions initiated by system devices coupled to the global bus are on-going.

Abstract: A method for detecting nets physically changed and electrically affected by a design ECO includes steps as follows. An ECO is executed on an IC design to produce a post-ECO IC design. A first group of nets of the IC design physically changed by the ECO is identified by comparing a pre-ECO database with a post-ECO database. A pre-ECO design SPEF file of the IC design is parsed with a script to identify a second group of nets in the pre-ECO database based on the first group of nets, the second group of nets being coupled to the first group of nets. The second group of nets is pre-ECO electrically affected nets. Parasitics for the first group of nets in the post-ECO database are extracted to generate a parasitic data file for the first group of nets. The parasitic data file is parsed with the script to identify a third group of nets in the post-ECO database based on the first group of nets, the third group of nets being coupled to the first group of nets.

Abstract: Embodiments of the invention include an electrical interconnection structure for connection to large electrical contacts. The electrical interconnection includes a semiconductor substrate having a conductive pad layer formed thereon. A dielectric layer having a plurality of elongate trenches is formed over the conductive pad layer such that the elongate trenches extend through the dielectric layer to the underlying conductive pad layer. Elongate conductive contacts are formed in the elongate trenches to establish electrical connections to the underlying conductive pad layer. The long axes of the elongate bar trenches can be arranged substantially parallel to the long axes of the slots formed in the copper pad. Alternatively, the long axes of the bar trenches can be arranged transversely to the long axes of the slots formed in the copper pad. In some embodiments, the conductive contacts are formed such that they establish electrical connection with sidewalls of the underlying conductive pad layer.

Abstract: An apparatus comprising an analog-to-digital converter, a compensation circuit, a partial response equalizer and a non-adaptive Viterbi decoder. The analog-to-digital converter may be configured to convert an input analog signal into a digital signal. The compensation circuit may be configured to generate an output signal by clipping the digital signal. The partial response equalizer circuit may be configured to shape the output signal into a pre-defined target with a delay operator. The decoder may be configured to calculate a minimum error between data in the output signal and other possible data sequences.

Abstract: A Gaussian family filter (e.g. an equiripple filter) comprises a first pole, a second pole, a third pole and a signal combiner. The first pole has a biquadratic low pass characteristic and is configured to provide a first low pass signal. The second pole is coupled to the first low pass signal, the second pole having a first-order low pass characteristic, and providing a second low pass signal and a high pass signal. The third pole is coupled to the second low pass signal and has a biquadratic low pass characteristic for generating a third low pass signal. The signal combiner is configured to combine the third low pass signal and the high pass signal to provide a combined signal.

Abstract: A delay line calibration circuit and method are provided in which a programmable master delay line drives a delay clock and has a propagation delay that is a function of a delay setting. A delay counter is clocked by the delay clock and has a delay count. A reference counter is clocked by a reference clock and has a reference count. A control circuit controls the delay and reference counters, compares a representation of the delay count to a representation of the reference count and responsively generates a modified value for the delay setting to reduce a difference between the representations of delay count and the reference count.

Abstract: A linear capacitor design providing shielding on all sides of the linear capacitor. In one aspect the capacitor provides a signal side metal layer substantially enclosed by a dielectric material which is, in turn, substantially enclosed by an upper and lower metal shield layer. in another aspect, the upper and lower shield metal layers may be coupled by a plurality of vias. In another aspect, a plurality of alternating intermediate layers provide signal side metal and shield metal separated by dielectric material such that each signal side layer is substantially enclosed by one or more shield metal layers. In another aspect, multiple intermediate signal side metal layers are conductively coupled to one another by a plurality of vias and multiple shield metal layers are conductively coupled to one another by a plurality of vias.

Abstract: A code efficient transfer method in response to a single host I/O request generates a single scatter gather list. The disk array controller transforms the single host I/O request into multiple physical I/O requests. Each of these multiple physical I/O requests uses the single scatter gather list to perform the data transfer operation. Each physical I/O request corresponds to the data transfer of one data stripe. The data stripe is an initial or header stripe of about 0.5K or a stripe of at least 64K.