Abstract: A method and system for facilitating communication between computer subnets are provided. One embodiment of the present invention comprises presetting buffers in an internal subnet, wherein the buffers help route external commands to a plurality of devices within the internal subnet. When a command from an external subnet is received by the internal subnet, the command is translated and sent to the proper internal device, as determined by the buffers. The command is then performed by the proper internal device. In another embodiment of the present invention, translation mapping are established for the internal subnet. When a command is received from an external subnet, the destination address associated with the command is translated to the address of the appropriate internal device, and the command is then sent directly to the internal device, which performs the command. By using either the buffer or translation mappings, the internal subnet appears to be a single device to the external subnet.

Abstract: A grooming switch comprises plural input ports for receiving multi-time-slot input signals and plural output ports for forwarding multi-time-slot output signals. At least five switching stages alternate between time switching and space switching. The first stage is connected to the input ports, and the last stage is connected to the output ports. Each intermediate stage is connected to two other stages. Collectively, these stages perform compact superconcentration of the input signals, copying and distribution of the compact superconcentrated signals, and unicast switching of the distributed signals to form the output signals, resulting in a grooming switch that is rearrangeably non-blocking for arbitrary multicast traffic.

Abstract: The invention may relate to a digital frequency adjuster for adjusting a first frequency of a first signal. The digital frequency adjuster may comprise a first digital delay line and a first control circuit. The first digital delay line may comprise a plurality of taps. The first digital delay line may be configured to (i) receive the first signal and (ii) generate a second signal. The first control circuit may be configured to control dynamic assertion of respective ones of the taps at a rate such that the second signal has a second frequency different from the first frequency of the first signal.

Abstract: A memory generation and placement flow system that receives a customer memory design and places the customer memory design within a customizable standardized integrated circuit design. The memory generation and placement flow system includes a memory librarian tool, a memory estimator tool, and a memory placer tool.

Abstract: A four point measurement technique for testing programmable impedance drivers such as the BZIO buffers contained in RapidChip® and ASIC devices. Specifically, two test pads are added for taking voltage measurements at additional points. By taking the additional voltage measurements and performing some calculation using Ohm's law, the error components of the testing process are effectively eliminated. The technique is suitable for use at wafer sort where additional device pads can be made available for contact with the automated test equipment (ATE) used in the manufacturing test environment.

Abstract: A circuit generally including a control function and a checksum function is disclosed. The control function may be configured to assert (i) a start signal in response to a signal having a predetermined sequence of values matching an entry value and (ii) a stop signal in response to the signal matching an exit value. The checksum function may be configured to (i) generate a checksum value for the signal between assertions of the start signal and the stop signal and (ii) generate a result signal in response to comparing the checksum value with an expected value.

Abstract: A latch based random access memory includes an input data register; an input data buffer coupled to the input data register; a latch array coupled to the input data buffer; and a latch array bypass multiplexer for selecting one of the input data buffer and the latch array in response to a memory scan mode signal to generate a first data output of the latch based random access memory from the input data buffer during logic scan testing and a second data output of the latch based random access memory from the latch array during memory scan testing.

Abstract: A electronic design automation tool, apparatus, method, and program product by which design requirements for an intended semiconductor product and the resource definitions of a semiconductor platform are input. From the design requirements and the resource definitions, parameters specific to clocking are derived, e.g., clock property information, clock domain crossing information, and clock relationship specification. The tool and method embodied therein validates the clocking parameters of the design requirements with the resource definitions and invokes errors if the parameters are not realizable. Once the desired clocking parameters are consistent with the actual clocking parameters, correct physical optimization constraints and timing constraints are generated for the clocks. An iterative process can achieve correct and minimal clocking constraints.

Abstract: A redundant array of solid state disk drives is provided among the storage devices controlled by a storage controller. The solid state disk drives may serve as a level 2 cache using standard multi-level cache management algorithms. The solid state disks may share a drive channel with other storage devices or may have a dedicated channel. Multiple solid state disk devices may also be provided to avoid single points of failure. With two solid state disks, the storage processor could maintain the cache data in both devices. If one device fails, the other could be used to maintain data services. With two or more devices, other Redundant Array of Independent Disks organizations may be used to improve data-to-metadata ratio while maintaining fault tolerance. Using these Redundant Array of Independent Disks techniques, the plurality of solid state disks may then be organized as a single level 2 cache volume that serves as a second level cache for a storage controller.

Abstract: A system and method for reading and writing in a multilevel optical data system is disclosed. The system provides control signals for timing acquisition, level calibration, DC control, AGC, equalizer training and data synchronization. The user data is ECC protected and optionally convolutionally encoded before being combined with the control signals in an information block. The multilevel information block can be written to an optical disc as a series of multilevel marks. The optical disc may also contain an Address in Pregroove signal (AIP) to facilitate synchronization during writing of an information block. The AIP signal has an integer number of address frames per information block.

Abstract: The present invention is an apparatus and system for reducing bondpad capacitance of an integrated circuit. Circuitry of the present invention may produce a negative capacitance approximately equal in magnitude to the capacitance associated with the bondpad and thereby effectively eliminate the bondpad capacitance. Values of the components of the circuitry may be selectively and independently chosen to synthesize a variable range of negative capacitance and thus produce a negative capacitance approximately equal in magnitude to a unique capacitance associated with the bondpad of a variety of integrated circuits.

Abstract: A p-type polysilicon resistor formed in the inter-level dielectric layer contains an implanted diode. A positive voltage applied to the diode modulates the depletion region of the diode and changes the absolute resistance of the p-type polysilicon resistor. This modulation occurs not only horizontally, but also vertically. The fact that the tunable resistor is a p-type polysilicon resistor means that this structure can easily be integrated into the process since polysilicon is used as a gate material for basic CMOS processing.

Abstract: A method and system for detecting defects in a physical mask used for fabricating a semiconductor device having multiple layers is disclosed, where each layer has a corresponding mask. The method and system include receiving a digital image of the mask, and automatically detecting edges of the mask in the image using pattern recognition. The detected edges, which are stored in a standard format, are imported along with processing parameters into a process simulator that generates an estimated aerial image of the silicon layout that would be produced by a scanner using the mask and the parameters. The estimated aerial image is then compared to an intended aerial image of the same layer, and any differences found that are greater than predefined tolerances are determined to horizontal defects. In addition, effects that the horizontal defects may have on adjacent layers are analyzed to discover vertical defects.

Abstract: A method for implanting ions in a semiconductor is disclosed. The method includes implanting indium ions into a substrate of a semiconductor material of the semiconductor device for a first time period. The method also includes implanting boron ions into the substrate for a second time period, wherein the first time period is initiated prior to the second time period.

Abstract: A system, apparatus and/or method is provided for fabricating an integrated capacitor during the fabrication of a transistor employing chemical mechanical polishing of a gate electrode of the transistor. Components of the integrated capacitor, particularly the lower electrode of a parallel plate capacitor in one form thereof, and an outer plate of a cylindrical-like capacitor in another form thereof, are defined by the polish stop layer during chemical mechanical polishing (CMP) of a gate of the transistor. According to an aspect of the subject invention, the polish stop layer may be an oxide or a nitride.

Abstract: A method and computer program product for early physical design validation and identification of texted metal short circuits in an integrated circuit design includes steps of: (a) receiving as input a representation of an integrated circuit design; (b) receiving as input a physical design rule deck that specifies rule checks to be performed on the integrated circuit design; (c) generating a specific rule deck from the physical design rule deck wherein the specific rule deck includes only physical design rules that are specific to one of identifying texted metal short circuits in the integrated circuit design and power distribution and input/output cell placement in the integrated circuit design; and (d) performing a physical design validation on the integrated circuit design from the specific rule deck.

Abstract: Methods and associated structure to improve disk capacity utilization in the context of size coercion and COD space reservation techniques applied in a storage system. One aspect hereof provides that the size coercion computations to reduce (round down) the capacity of one or more disk drives in a storage system are performed prior to reservation of disk space for use in configuration-on-disk (COD) techniques. Performing coercion computations and configuration prior to COD space reservation prevents the COD reservation processing from causing un-necessary waste of physical capacity of the coerced disk drives.

Abstract: The present invention provides for a method and computer program product for handling timeout in a standard RPC connection. First, a client establishes a connection with a server with unique identification. After submitting an RPC request, the client system will periodically make secondary requests to the server to determine if the server is still actively processing the primary RPC request. If the secondary request is processed successfully and the server indicates that the primary request is still in progress, the client will continue to wait until either the primary request completes or enough time elapses to warrant another secondary request. The success of the secondary request hinges on finding a match of identification for the primary and secondary requests. If the secondary request fails, this failure is treated as a sign that there is either a network or a server problem, and the client is triggered into taking appropriate corrective action.

Abstract: A semiconductor package construction aimed at improving thermal performance. A heatspreader is provided having a metal alloy preform attached to it already. Then, a few dots of conductive epoxy are dispensed around the die. The heatspreader with the preformed metal alloy is pressed on the adhesive and then the part is cured. By coupling the die to the heatspreader with conductive epoxy, the die is constrained from warping. By removing the necessity of coating the die, the cost of fabrication is reduced. There is only a very marginal cost increase in the back end for dispensing the dots. For this, the process and equipment already exists in the backend. By reducing die backside warpage due, the die remains in good contact with the heatspreader, thus improving thermal performance.

Abstract: Methods and structure for storing volume and other configuration information on all disk drives of a volume group and for performing pre-merge operations to inform a user of the pending availability of the identified volumes. Configuration information has been historically stored in two distinct areas of configuration information on disk drives—a volume information area and an “other” information area. Aspects of the invention provide for storing all configuration information in the “other” information area. All disks of a system therefore include all configuration information relating both to volumes and to pseudo volume. A pre-merge operation is performed when each disk drive is inserted into a storage system to present new volume information to a user. When the last disk drive of a volume group is inserted, the user may select new volumes to be imported into the system.