Abstract: A system and method for collecting and analyzing integrated circuit test vehicle test data by identifying various blocks of circuitry through at least two different intersecting test paths. In one embodiment, the process test circuits may be arranged in a matrix format and connected so that they may be tested along rows or columns. When a failure along a specific row and a specific column is identified, the process test circuit at the intersection may be identified as the failure point.

Abstract: Test circuitry for supporting real-time testing of data exception software may be included on an integrated circuit. The circuitry supports the identification of a data unit or data group other than a next data unit or data group to be transferred in a data sequence and the generation of an erroneous data verification parameter that does not verify the data content of the identified data unit or data group. The identified data unit or group is later transmitted with the erroneous data verification parameter in real-time following the transmission of other data units and/or data groups having valid data verification parameters. In this manner, a data receiver may be tested to verify the detection of a data content error in real-time and the execution of the software or firmware for processing an exception may be verified. Circuitry for implementing the method of the present invention may be included on the substrate of an integrated circuit.

Abstract: The present invention is directed to a timing abstraction and partitioning strategy for integrated circuit design. A method for designing an integrated circuit may include monitoring user interaction with logical blocks during a function design process of an integrated circuit. Indications of timing properties are derived during the functional design process.

Abstract: A method of making a reticle. Design data, i.e., GDSII data is read in, then a scribe or frame is built, and the design is placed in the scribe. Then, Boolean operations, sizing, OPC corrections and phase shifting are performed, as needed, perhaps using third party tools. Then, the GDS data is sorted, and a new GDS hierarchy is created where each mask layer can be generated as one mask making pattern, i.e., new cells are created representing each masking image location on the reticle, each new cell is placed in a topcell, then a gds2 file is produced where the gds2 file can be used to create a reticle or can be used to create reticle making data.

Abstract: An SIP for performing a plurality of hard and soft functions comprises standard IC die and custom platforms mounted to a substrate. Die are identified for each standard hard function, such as memory, processing, I/O and other standard functions and one or more user-configurable base platforms are selected that, when configured, execute the custom soft functions. Optionally, the substrate is laminated to the die and the platforms are attached to the substrate. Testing is performed by defining the configured base platforms coupled to logic representing the die and their connections and performing placement and timing closure on the combination.

Abstract: A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions are grouped for assignment to FPGA modules. The non-memory programmable functions are synthesized to ASIC modules, and the memory programmable functions are synthesized to FPGA modules. Placement, signal routing and boundary timing closure are completed and the platform is configured by adding metallization layer(s) to configure the ASIC modules and creating a firmware memory to configure the FPGA modules. An over-provisioning feature in the FPGA modules permits post-fabrication alteration of logic functions.

Abstract: A decoder for access data stored in n memories comprises a function matrix containing addresses of the memory locations at unique coordinates. A decomposer sorts addresses from coordinate locations of first and second m×n matrices, such that each row contains no more than one address from the same memory. Positional apparatus stores entries in third and fourth m×n matrices identifying coordinates of addresses in the function matrix such that each entry in the third matrix is at coordinates that matches corresponding coordinates in the first matrix, and each entry in the fourth matrix is at coordinates that matches corresponding coordinates in the second matrix. The decoder is responsive to entries in the matrices for accessing data in parallel from the memories.

Abstract: A method of operating a modem generally comprising the steps of (A) transmitting an invalid signal from the modem at each of a plurality of settings for an echo cancelling hybrid of the modem, (B) calculating a plurality of merit values each in response to an echo signal received by the modem in response to the invalid signal, and (C) adjusting the echo cancelling hybrid to a particular setting of the settings determined from the merit values.

Abstract: Fabrication of electronic devices in the “metal layers” of semiconductor devices. Each metal layer includes a dielectric layer that supports a conductive layer, which includes electrically conductive pathways and electronic devices. The metal layers are stacked on top of each other such that the dielectric layers separate the adjacent conductive layers. The electronic devices may be passive devices such as resistors. The resistors are formed by depositing metal onto the dielectric layer and then implanting the metal with oxygen. The conductive layer may be formed of materials such as copper and aluminum.

Abstract: An integrated circuit layout is provided, which includes a base platform for an integrated circuit, a processor hardmac and a support memory. The base platform includes a memory matrix having leaf cells arranged in rows and columns. Each column of leaf cells has interface pins that are routed to a common matrix edge and have a common pin order along the matrix edge. The processor hardmac is placed along the memory matrix and has a hardmac edge adjacent the memory matrix edge and a plurality of interface pins for interfacing with corresponding interface pins of the memory matrix. The interface pins of the processor hardmac have the same pin order along the hardmac edge as the interface pins along the matrix edge. The support memory for the processor hardmac is mapped to a portion of the memory matrix along the hardmac edge.

Abstract: A system and method for collecting and analyzing optical inspection results obtained during the manufacturing process and comparing those results to actual functional results of a specially designed test vehicle integrated circuit. The test vehicle integrated circuit allows failures to be localized to very small areas, which allows more accurate correlation between inspection faults and functional failures. The correlation of inspection faults to actual functional failures is used to change the sensitivity settings for an optical inspection system to more accurately detect defects that are likely to be functional failures.

Abstract: An apparatus comprising an input section, a first delay circuit and a second delay circuit. The input section may be configured to present a first intermediate signal by selecting either (i) an input clock signal or (ii) a feedback of an output signal. The first delay circuit may be configured to generate a second intermediate signal by delaying the first intermediate signal by inserting one of a plurality of fixed delays in response to a first control signal. The second delay circuit may be configured to generate the output signal by delaying the second intermediate signal by inserting a programmable delay in response to a second control signal.

Abstract: Systems and methods for analyzing data passing between an SAS/SATA device and a plurality of other devices are presented. A system includes a plurality of physical interfaces configured for passing data between the SAS/SATA device and the other devices. The system also includes a test interface, or test PHY, configured for coupling to the physical interfaces for analysis of the data passing through those physical interfaces. The test PHY may be integrally configured with the SAS/SATA device and may substantially minimize alteration of characteristic impedance caused by external analysis of the data. The system may also include a multiplexer for selectively coupling the PHYs to the test PHY.

Abstract: An implantation method to improve ESD robustness of thick-oxide grounded-gate NMOSFET's in deep-submicron CMOS technologies. Based on standard process flow in DGO, a thick gate-oxide ESD device is improved. Instead of using the standard I/O device, the ESD device uses the thin-oxide N-LDD implantation, and thus its ESD robustness is enhanced. This is performed by updating the logic Boolean operations of thick gate-oxide and thin gate-oxide N-LDD before fabricating the masks. In TGO, the intermediate-oxide ESD uses thin-oxide N-LDD implantation, and the thick-oxide ESD uses intermediate-oxide N-LDD implantation.

Abstract: A semiconductor package comprising a packaging substrate, a semiconductor die mounted with the substrate, a heatspreader, and a multi-layer heat transfer element arranged between the semiconductor die and the heat spreader to enable thermal communication between the die and the heat spreader is disclosed. The multi-layer heat transfer element includes a core spacer element sandwiched between a first layer of thermally conductive reflowable material and a second layer of thermally conductive reflowable material. Also disclosed are methods for forming such semiconductor packages and for forming multilayer heat transfer elements.

Abstract: A metal-insulator-metal capacitor is embedded in an interconnect layer of an integrated circuit (IC). The interconnect layer has a cavity, and the capacitor is formed in the cavity with one of the plates of the capacitor integral with a conductive layer of the interconnect layer, so the capacitor plate electrically communicates with the interconnect layer. The interconnect layer has multiple conductive layers, including a layer, such as aluminum, that is subject to deformation at certain temperatures during fabrication of the IC, and the cavity extends through this layer. A remaining conductive layer of the interconnect layer defines one of the capacitor plates, and a dielectric layer and another capacitor plate are formed thereon within the cavity. Via interconnects of about the same length electrically connect to the top plate and through the interconnect layer to the bottom plate.

Abstract: An abrasive electrolyte solution adapted for thinning a layer on a substrate without contaminating the substrate. The abrasive electrolyte solution includes an electrically conductive fluid that is substantially free of materials that are reactive within a desired operating voltage potential range, and substantially free of materials that inhibit desired reactions within the desired operating voltage potential range. Also included are abrasive particles that have a size that is small enough for the particles to substantially remain in suspension in the electrically conductive fluid, and large enough for the particles to provide a desired degree of erosion of the layer on the substrate when the abrasive electrolyte solution is forced against the layer on the substrate.

Abstract: An integrated video decoding system with spatial/temporal video post-processing is disclosed. The integrated video decoding system includes a video decoder for decompressing an input data stream, and an integrated post-processing stage coupled to the video decoder. According to one aspect of the present invention, the integrated post-processing stage combines a temporal filter, a de-interlacer, and optionally a deblocking filter. The integrated post-processing stage further utilizes a single memory system used by the temporal filter and the de-interlacer.

Abstract: A method of placing a clock signal supply network in a design representation for an integrated circuit. The design representation may comprise a plurality of clockable circuit cells. The method may comprise identifying a first of the clockable circuit cells in the design representation. The method may further comprise identifying a second of the clockable circuit cells in the design representation. The second clockable circuit cell may have a clock timing dependent relation relative to the first clockable circuit cell. The method may further comprise configuring the clock signal supply network. The clock signal supply network may be configured to supply respective clock signals to the first and said second clockable circuit cells. The clock signal supply network may be configured to route the respective clock signals such that a timing difference between the respective clock signals is protected from process, voltage and temperature (PVT) influences.

Abstract: An apparatus for memory error control coding comprising a first circuit and a second circuit. The first circuit may be configured to generate a multi-bit digital syndrome signal in response to a read data signal and a read parity signal. The second circuit may be configured to (i) detect an error when the bits of the syndrome signal are not all the same state and (ii) generate an error location signal in response the syndrome signal. The error location signal may be generated in response to fewer than all of the bits of the syndrome signal.