Abstract: Creation and detection of synchronization marks for a multilevel data storage medium is disclosed. A sequence of symbols is generated and the sequence of symbols is written to the multilevel data storage medium. A corresponding sequence may be generated by a detector and correlated with read data to detect the synchronization mark.

Abstract: The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set. The restructuring set includes restructuring cells with an initial cell. The restructuring set is adapted to accept additional cells identified as restructuring cells. The candidate set is adapted to include candidate cells, where each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set. The candidate set is adapted to remove candidate cells from the candidate set. The restructuring set is adapted to accept selected removed candidate cells as identified restructuring cells if a corresponding parameter is included in the set of parameters.

Abstract: A system for RTL test insertion in an integrated circuit layout pattern includes a core module, a test wrapper, and a smart wrapper. The core module describes a function defined by logical elements, interconnections between logical elements, input pins and output pins. The test wrapper is adapted to encapsulate the core module and to create test pins representing the core module. The smart wrapper is adapted to encapsulate the test wrapper and to assign the test pins to a non-asserted state. The smart wrapper is adapted to place an assertion on one or more of the test pins for static or dynamic testing of the integrated circuit layout pattern.

Abstract: A pre-diffused array of core memory cells is provided in a metal programmable device. Multiple control block versions of interface logic are also provided and placed around the memory core. Contact points for each control block are brought to the surface of the wafer using a via. The appropriate interface logic is selected by connecting the metal layer to the appropriate surface contacts to access the core memory cells. The application-specific circuit, including memory configuration and memory interface type, is programmed with the metal layer.

Abstract: Methods and systems for optimizing data mirroring operations are disclosed. One or more data channels can be selected from among a plurality of data channels associated with a data-processing system, such that the selected data channel or data channels can comprise a data channel that is the least occupied data channel among the plurality of data channels. A plurality of data mirroring operations can then operate simultaneously on the selected data channel or data channels, in response to selecting the data channel form among the plurality of data channels, thereby optimizing data mirroring operations associated with said data-processing system.

Abstract: An apparatus comprising a clock generation circuit, a detect circuit and a select circuit. The clock generator circuit may be configured to generate an output clock signal in response to a control signal. The detect circuit may be configured to generate a detect signal in response to (i) the output clock signal and (ii) an input signal. The select circuit may be configured to generate the control signal by selecting (i) a first input when in a first mode (ii) the detect signal when in a second mode. The first and second modes are selected in response to a selection signal.

Abstract: An apparatus for routing power between a set of power supply taps of an automated tester and power connections on an integrated circuit under test, where the integrated circuit belongs to a family of integrated circuits that have a common power connection layout and different power connection voltage requirements. An interface board having first electrical contacts disposed in the common power connection layout makes electrical connections to the power connections of all integrated circuits belonging to the family of integrated circuits. The first electrical contacts are electrically routed to second electrical contacts disposed in a standardized configuration. A power personality card having third electrical contacts makes electrical connections to the second electrical contacts of the interface board.

Abstract: An integrated circuit, or portion thereof, such as a CMOS device, includes an epitaxially grown dielectric on a silicon carbide base. The epitaxially grown dielectric forms a gate dielectric and the silicon carbide base serves as a channel region for the CMOS device. In various embodiments, the epitaxially grown dielectric may be a crystalline carbon or carbon-containing film.

Abstract: A method and system for automatically instantiating built-in-system test (BIST) modules in memory designs is disclosed. The method and system include providing a server over a network that integrates a set of design tools, including an automated front-end software process and an automated back-end software process. According to the method and system, a user may access the server over the network and enter a request for a memory design. The front-end software process is then executed to automatically generate a netlist of a BIST from the user request. Thereafter, the back-end software process is executed to automatically generate a placement and route view of the BIST.

Abstract: A lithographic scanner collects surface height information concurrently with conducting a lithographic scan process. A defect identification module identifies wafers having a surface height metric greater than a determined threshold. The identified wafers may be separated for rework to correct the surface defects such as hotspots and improve manufacturing yield without requiring additional equipment. In one embodiment, the surface height metric is a maximum variation from a moving average surface height. In one embodiment, yield data is correlated with surface height information to determine a threshold value corresponding to defective circuit die.

Abstract: A solid state disk drive is provided among the storage devices controlled by a storage controller. The solid state disk drive may serve as a level 2 cache using standard multi-level cache management algorithms. The solid state disk may share a drive channel with other storage devices or may have a dedicated channel.

Abstract: A system and method are disclosed for reading a multilevel signal from an optical disc. The method includes reading a raw analog data signal from a disc using an optical detector and adjusting the amplitude of the raw analog data signal. A timing signal is recovered from the amplitude adjusted analog data signal and correction is made for amplitude modulation of the raw analog data signal by processing the raw analog data signal and the timing signal.

Abstract: A method for determining component patterns of a raw substrate map. A subset of substrate patterns is selected from a set of substrate patterns, and combined into a composite substrate map. The substrate patterns are weighted. The composite substrate map is compared to the raw substrate map, and a degree of correlation between the composite substrate map and the raw substrate map is determined. The steps are iteratively repeated until the degree of correlation is at least a desired degree, and the weighted subset of substrate patterns is output as the component patterns of the raw substrate map.

Abstract: An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph the elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-first-search method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method accounts for coupling capacitance between interconnects.

Abstract: An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric region formed over a channel region. A doped region is formed between a top portion and a bottom portion of the dielectric region. This doped region includes a suitable electron affinity material. A gate electrode is connected with the top of the dielectric region. In some embodiments, suitable electron affinity materials are introduced into the doped region using implantation techniques. In another embodiment, the electron affinity material is introduced into the doped region using plasma treatment of the dielectric region and the redeposition of additional dielectric material on top of the dielectric region and doped region.

Abstract: A test vehicle for evaluating a manufacturing process for integrated circuits that uses a more space efficient layout of library driving cells arranged to produce circuits that exercise many interconnections that may be designed at the minimum design parameters of a manufacturing process. The cells can be configured to operate as ring oscillators increasing the effective circuit frequency of the test module allowing higher frequency circuit testing, and shortening the time it takes to perform life cycle testing. Visibly marking cells, combined with electrically isolating error prone circuit segments makes, identifying defects much more efficient. The accessibility of many testing methods allows quick location of root cause failures, which allows improvements to be made to the manufacturing process.

Abstract: The present invention provides a system and method for monitoring a short clock cycle on a semiconductor chip. The system includes a phase-locked loop (PLL) for receiving a reference clock as input and for outputting a PLL clock out. The system includes a delay-locked loop (DLL) for receiving the PLL clock out as input and for outputting a DLL phase offset clock. The DLL is locked to a frequency of the PLL clock out. The system may include an edge comparator for receiving the PLL clock out and the DLL phase offset clock as input. The edge comparator is suitable for monitoring each edge of the PLL clock out and each edge of the DLL phase offset clock, and for reporting a short clock cycle when an edge of the PLL clock out comes before an edge of the DLL phase offset clock.

Abstract: A method for integrating a first integrated circuit design having first layers and a second integrated circuit design having second layers into a common reticle set. The second integrated circuit design has a given number of second layers and the first integrated circuit design has less than the given number of layers. At least one of the first layers is duplicated to produce at least one duplicated first layer until the first integrated circuit design has the given number of layers. The first layers and the at least one duplicated first layer are mapped to a modified first integrated circuit design having the given number of first layers. A reticle set is fabricated to include the given number of first layers and second layers, using the modified first integrated circuit design and the second integrated circuit design.

Abstract: An integrated circuit (IC) includes a CMOS device formed above a semiconductor substrate having ions therein that are implanted in the semiconductor substrate by an ion recoil procedure. The IC preferably, but not necessarily, incorporates sub-0.1 micron technology in the CMOS device. The implanted ions may preferably be germanium ions. A strained-silicon layer is preferably, but not necessarily, formed above the ion-implanted layer of the semiconductor substrate. The strained-silicon layer may be formed by a silicon epitaxial growth on the ion-implanted layer or by causing the ions to recoil into the semiconductor substrate with such energy that a region of the semiconductor substrate in the vicinity of the surface thereof is left substantially free of the ions, thereby forming a strained-silicon layer in the substantially ion-free region.

Abstract: The present invention is an apparatus and method for protecting against drive anomaly errors while optimizing random read performance. Data block persistency is explicitly verified when a data block is written. Data block integrity and location checks are performed by reading data from a single drive. Through such a process, reading of metadata from a second drive is not required, thus decreasing the drive I/O workload. In an example of the invention, a combination of a CRC and a location tag interleaved as metadata along with user data on a single drive may be employed to perform a read operation in accordance with the present invention.