Abstract: An arrangement and method for fabricating a semiconductor wafer which utilizes a nonaqueous solvent rinse is disclosed.

Abstract: A memory management unit (MMU) for a device controller that provides enhanced functionality while maintaining a small physical size or footprint, such that the die size required to manufacture the memory management unit circuitry within the device controller integrated circuit device remains small notwithstanding such enhanced functionality. This compact/tiny MMU provides virtual memory addressing and memory error detection functionality while maintaining a small physical die size. The small physical die size with enhanced functionality is obtained by improvements in translating virtual to physical addressing without use of extensive translation tables, which themselves would otherwise consume memory and associated die real estate. In addition, the MMU allows a firmware image containing code and data segments to be run-time swapped between internal shared context RAM and external memory.

Abstract: A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.

Abstract: A computer storage enclosure may comprise a mounting chassis and a computer drive apparatus. The mounting chassis may have a plurality of computer drive guides, a plurality of cam pins, and a mounting chassis disengagement ramp. The computer drive apparatus may include a computer drive, a plurality of shoulder screws, and a computer drive handle. The computer drive apparatus may be mounted on the mounting chassis utilizing the shoulder screws guided by the computer drive guides and secured by the computer drive handle, the cam pins, and the shoulder screws. The computer drive apparatus may include a blade drive and be hot-swappable.

Abstract: A system, apparatus and method for generating and validating extracted timing model files, such as macro library files, are disclosed. A user interface or data template is provided to an engineer that allows for the population of data within particular fields related to timing characteristics of an IP block, cell or core. An extracted timing model file is generated and a validation procedure is performed. This validation procedure may include comparing the information with the file to a test bench have a plurality of test points. In particular, data provided by the engineer is checked against multiple criteria to ensure that this data is valid and/or falls within an appropriate value range constraints. After the validation procedure has completed, the engineer is provided a summary of the validation results.

Abstract: A flow-based FIFO sub-system for a disk formatter in a data processing system that performs data width conversion. The sub-system has a first FIFO unit having a first width interfacing to a first bursting channel, and a second FIFO unit having a second width interfacing to a second bursting channel, the second width not being a multiple of the first width and the first width not being a multiple of the second width. Data width conversion is performed between the first FIFO unit and the second FIFO unit to convert data moving from the first FIFO unit to the second FIFO unit from the first width to the second width, and to convert data moving from the second FIFO unit to the first FIFO unit from the second width to the first width. The sub-system also includes an Error Correcting Code interface between the first FIFO unit and the second FIFO unit for performing in-line correction.

Abstract: A method and system prioritizes frames to be transmitted from a local node to a remote node on a Fibre Channel Arbitration Loop. The frames are placed in context queues. Each kind of context queue is assigned a priority. A determination of a set of transmit frame types is made. A user, an external device, or code may determine the number of transmit frame types in the set. A priority is assigned for each of the transmit frame types in the set. The transmit frame types may be determined by context type. The frames are prepared for transmission. The queues are examined by a suitable method to determine order of transmission. The transmit prioritizer preferably comprises five three-entry deep queues in which the prioritizer places valid contexts classified by transmit frame type. Queued contexts are selected for outgoing frame transmission by a prioritization algorithm aimed at saving the current fibre channel loop tenancy to maximize performance whenever possible.

Abstract: The present invention is a method and apparatus in a data processing system that includes a Voice over Internet Protocol (VoIP) communication system for improving transmit and receive data paths. The communication system includes a digital signal processing unit. The digital signal processing unit includes a mandatory coder/decoder (codec) that does not include an internal packet loss concealment (PLC) function, an internal voice activity detection (VAD) function, an internal comfort noise generation (CNG) function, or an internal discontinuous transmission generation (DTX) function. The digital signal processing unit also includes an enhanced codec that includes any combination of the following modules all internal to the enhanced codec: internal packet loss concealment (PLC) function, a voice activity detection (VAD) function, a comfort noise generation (CNG) function, and a discontinuous transmission generation (DTX) function.

Abstract: A method and circuit for performing CRC calculations permits variable width data input. Preferably, multiple CRC calculations are performed in parallel, each CRC calculation involving a different number of data bits from the data word and terminating within one clock cycle. The CRC polynomial is preferably incorporated into the hardware for each CRC calculation.

Abstract: The present invention provides a method of design based process control optimization. In an embodiment, the method of design based process control optimization includes creating a circuit layout database including a design rule set. At least one algorithm is employed to query the circuit layout database to calculate at least one process specification limit. The method includes comparing the calculated at least one process specification limit with at least one predefined technology process tool capability to determine if the calculated at least one process specification limit allows for a manufacturable process. If the calculated at least one process specification limit does not allow for the manufacturable process, the limit may be re-optimized.

Abstract: The present invention is a method for data path voltage and temperature compensation. The method includes configuring an offline data path to match an online data path. The method further includes compensating the offline data path for voltage and temperature variation. The method further includes swapping the offline data path with the online data path. Further, swapping occurs automatically without interruption of data flow along the data paths.

Abstract: The present invention is directed to a method of an adaptive procedure table which is capable of providing default behaviors for each procedure if a corresponding procedure is not defined or has been removed from a software build. The default behaviors for each procedure may be defined in a template file provided by a developer before a compile time of software. The present invention may permit a module that defines the implementation of a procedure to be removed from the software build without requiring source code changes. As such, the developer may be allowed to remove or add certain features from a compiled program without introducing compile time or link time errors.

Abstract: The present invention is directed to methods for defining and naming iSCSI targets using volume access and security policy. In an exemplary aspect of the present invention, a method for defining an iSCSI target using volume access and security policy may include the following steps. One or more volumes of a network entity may be first mapped to an initiator. The mapping defines the unique Logical Unit Number for the volume to an initiator. Then, a security level may be defined for access to each volume accessed by the initiator. The subset of mappings for each initiator may be given any unique name. Next, the mapping and security subsets may be used to define the fully qualified targets with which the initiator may open a session.

Abstract: A semiconductor chip is provided which includes active and inactive IP cores. The spaces on the metal layer associated with the inactive IP cores includes voltage contrast inspection structures. The voltage contrast inspection structures serve to provide improved planarization of the metal layer and provided improved inspection capabilities.

Abstract: A method for implementing test generation for systematic scan reconfiguration in an integrated circuit is presented. The method may comprise: defining at least one set of detectable faults; setting an SAS decoder configuration, the SAS decoder configuration including a don't-care bit; generating an ATPG pattern; and applying the ATPG pattern to one or more scan chain segments having a segment address associated with the SAS decoder configuration.

Abstract: The present invention is directed to a system and method for supporting an alternative peer-to-peer communication over a network in a SAS cluster when a node cannot communicate with another node through a normal I/O bus (Serial SCSI bus). At startup, driver may establish the alternative path for communication but may not use it as long as there is an I/O Path available. In the present invention, two types of P2P calls, such as event notification calls and cluster operation calls may be supported.

Abstract: The present invention is directed to a sequential tester for longest prefix search engines. The tester may include a longest prefix search engine, an inputs generator for providing a nearly random flow of input commands to the longest prefix search engine and for outputting a floating rectangle which may represent a search table of the longest prefix search engine, a coding module for providing address and prefix information to the longest prefix search engine, a mapping module for providing data information to the longest prefix search engine, a super search engine for performing super search operations, and an analyzer for computing predicted outputs of the longest prefix search engine and for comparing the predicted outputs with actual outputs computed by the longest prefix search engine.

Abstract: A continuous-time domain Decision Feedback Equalizer (DFE) for use in a serial communication channel comprises in one embodiment a summer, a decision circuit, a capture flip-flop (FF) and an N-th order active filter. The DFE and its active filter operate in continuous time to give improved performance over a discrete-time DFE. In one embodiment involving a first-order active filter, the capture FF is outside the continuous-time negative feedback loop of the DFE and involves a differential signal amplifier. In another embodiment, the capture flip-flop is inside the DFE loop, and in a third embodiment the decision circuit comprises a comparator.

Abstract: The present invention provides a device and method for mitigating performance degradation caused by SATA drives attached to a SAS domain. In one of the embodiments of the present invention, a SATA degradation mitigation device (“SDMD”) is installed between a SAS domain and one or more SATA drives. The SDMD effectively reduces congestion on intermediate links by buffering SATA data and transmitting the data at a rate which is higher than the rate at which the SATA data is received from a drive. Conversely, write data from the SAS domain may be buffered at the SDMD at a higher rate and subsequently sent to the SATA drive at a lower rate. This SATA data buffering and subsequent increase in data rate improves the overall efficiency of a SAS domain storage system by reducing data congestion arising out of low-performance SATA drives clogging the intermediate links.

Abstract: Multiple inductor structures and methods for providing low mutual inductance between the inductors are described. In various embodiments of the invention, the polarities of the inductors are positioned such that parasitic mutual inductance is reduced by causing electro-magnetic fields to at least partially cancel resulting in a reduction in interference between the inductors. The polarities of the magnetic fields produced by each inductor are opposite to each other so that at least a partial cancellation results when the fields interfere with each other.