Abstract: One aspect of the present invention concerns a method for controlling the frequency of oscillation of a local clock signal comprising the steps of (A) generating the clock signal in response to a first control signal, (B) generating the first control signal in response to one of a plurality of adjustment signals selected in response to a second control signal and (C) generating the second control signal in response to a comparison between a local timestamp and an external timestamp.

Abstract: A method and apparatus for using and combining sub-frame processing and adaptive jitter-buffers for improved voice quality in voice-over-packet networks. Data is placed in a jitter buffer, where the data has a frame-length consisting of a plurality of samples. Some of the samples are placed in the DMA buffer, and some of the samples are placed in the back-up buffer. Samples are read out of the DMA buffer, and samples are moved from the back-up buffer to the DMA buffer.

Abstract: System and methods are disclosed for load balancing Input/Output (IO) commands to be executed by one or more disk drives from an array of disk drives. Systems and methods disclosed herein use one or more properties, such as disk drive RPM, disk drive cache, command queue lengths, real-time drive data, and head position to provide load balancing of Input/Output commands.

Abstract: Multiple matches of words in a content addressable memory are detected by identifying each match of the input word to a word in the memory, and generating a representation of a relationship OR (xi AND xj), where xi=x1, x2, . . . xN?1, xj?xi+1, xi+2, . . . xN, and x1, x2, . . . , xN are the compare results of the individual words in the memory to the input word. A representation of at least one match is identified by generating a representation of a relationship x1 OR x2 OR x3 OR . . . OR xN. The apparatus comprises a hierarchy of logic that carries a general match representation indicating at least one match between the input word and all of the memory words, and a multiple-match representation indicating multiple matches between the input word and the words in the memory.

Abstract: A system and method are provided for accelerating development and debug of a printed circuit board (PCB) designed for use with a platform ASIC in advance of availability of a prototype sample of the platform ASIC. Aspects of the invention include a pin-out adapter card that implements a predefined pin-out of the ASIC and that hosts FPGA logic resources for emulating I/O functionality and some (or all) of the ASIC core logic; a PCB designed for use with the platform ASIC, wherein the PCB includes the predefined ASIC pin-out for eventually mating with the ASIC; and a socket having mating connectors on both sides for mating with the ASIC pin-out on the PCB and to the ASIC pin-out on the adapter card, respectively, for coupling the adapter card to the PCB, thereby enabling development and debug of the PCB prior to availability of ASIC samples.

Abstract: Noise and signal-to-noise ratio (SNR) estimation are relatively straightforward tasks. However, when SNR is small, systematic errors in measurement may result in over-estimation of SNR, which also occurs during runtime monitoring of SNR. Here, sufficient numbers of bits have been preassigned to each channel using QAM modulation scheme. Therefore, SNR relative to QAM lattice size depends on the noise margin and the desired (bit error rate) BER. If a relatively small margin is desired, similar measurement errors may result in over-estimation of SNR. Another problem that arises is that the variance of the noise estimator is relatively high. Therefore, SNR estimates may vary by several dB, and there is only 50% confidence in the usual estimators that the actual SNR value will not be worse than that estimated. Thus, a computationally efficient method for SNR estimation that also allows for specification of a confidence level in the estimates is provided.

Abstract: A method for motion estimation comprising the steps of (A) determining whether a cost of encoding one or more prediction parameters for a current search position is less than a current best cost, (B) when the cost of encoding the one or more prediction parameters for the current search position is greater than or equal to the current best cost, determining whether the current best cost is less than a minimum cost for encoding one or more prediction parameters of one or more remaining search positions and (C) ending the search when the current best cost is less than the minimum cost for encoding the one or more prediction parameters of the one or more remaining search positions.

Abstract: A method for deinterlacing a picture is disclosed. The method generally includes the steps of (A) generating a plurality of primary scores by searching along a plurality of primary angles for an edge in the picture proximate a location interlaced with a field of the picture, (B) generating a plurality of neighbor scores by searching for the edge along a plurality of neighbor angles proximate a particular angle of the primary angles corresponding to a particular score of the primary scores having a best value and (C) identifying a best score from a group of scores consisting of the particular score and the neighbor scores to generate an interpolated sample at the location.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a decoded video signal and syntax elements in response to an encoded bitstream. The second circuit may be configured to generate one or more overlay images in response to the syntax elements. The overlay images generally comprise graphical symbols representing the syntax elements of the encoded bitstream.

Abstract: A method for producing a chip is disclosed. A first step of the method may include fabricating the chip only up to and including a first metal layer such that a core region of the chip has an array of cells, each of the cells having a plurality of transistors. A second step generally involves designing a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the cells to form (i) a mixed-signal module and (ii) a digital module, the mixed signal module generating at least one analog signal and at least one digital signal. In a third step, the method may include fabricating the chip to add the upper metal layers.

Abstract: A method and system is provided for creating a tap controller in a slice for use during custom instance creation to avoid the need of a boundary scan synthesis tool. Aspects of the present invention include during slice creation, using a software tool to create a test access port (TAP) from slice resources; during instance creation, allowing a customer to design a custom chip using the software tool to select which structures to use on the slice; and based on the customer selections, reconfiguring at the instance level connections between the tap controller and the selected structures.

Abstract: A low-k interconnect dielectric layer is strengthened by forming pillars of hardened material in the low-k film. An E-beam source is used to expose a plurality of pillar locations. The locations are exposed with a predetermined power and exposure time to convert the low-k film in the selected locations to pillars having higher hardness and strength than the surrounding portions of the low-k film.

Abstract: A strained-silicon film is disclosed. A silicon-germanium film is made by ion implantation of germanium into an epitaxial silicon layer, preferably at a temperature in the range of 200 C to 400 C. The wafer is annealed in situ or optionally after implantation. A silicon film is applied to the silicon-germanium film in a conventional manner to create the strained-silicon substrate.

Abstract: A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a set of second buffers so each leaf is driven by an inserted buffer without timing violations, and moving the first buffer to a center of gravity of the set of second buffers.

Abstract: A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw.

Abstract: An RRAM design having linear BIST memory and rectangular BIST memory, the improvement comprising at least one of the linear BIST memory and the rectangular BIST memory formed only of flipflops and logic cells.

Abstract: A method for calibrating a center error signal in an optical disc system, comprising the steps of (i) measuring a peak-to-peak value of the center error signal, (ii) computing a nominal peak-to-peak value of the center error signal after locking to a particular track of an optical disc, (iii) computing the nominal peak-to-peak value of the center error signal for a run-out condition, and (iv) defining a calibration gain for the current value for the center error signal.

Abstract: A circuit for providing a bit string, the circuit including a plurality of commonly wired, substantially identical bit cells in a string, where each bit cell is designed to read as only one of a logical high and a logical low upon a given input, and each bit cell comprises a bit in the bit string. An enable line is associated with each of the bit cells, where each enable line has a fuse that is adapted to be activated upon application of a signal by a tester. Each bit cell is configured so as to be logically isolated from all others of the plurality of bit cells in the string when the fuse associated with the bit cell is activated. The circuit is adapted such that bit cells having fuses that are activated are logically removed from the bit string.

Abstract: A packaged integrated circuit including a package substrate having electrical contacts for receiving an integrated circuit. The integrated circuit is electrically connected to the electrical contacts of the package substrate. A stiffener is mounted to the package substrate, where the stiffener has a non-orthogonal cut out in which the integrated circuit is disposed. The edges of the cut out are disposed at no greater a distance from the corners of the integrated circuit than they are from the sides of the integrated circuit.

Abstract: A circuit for stabilizing soft bits in a bit stream, the circuit having a first register to receive an initial read of the bit stream, a second register to receive a subsequent read of the bit stream, a comparator to compare the initial read of the bit stream to the subsequent read of the bit stream, a third register to receive a comparison string having bits set in positions where the initial read of the bit stream and the subsequent read of the bit stream do not match, indicating a soft bit in the positions, and an accumulator to receive the comparison string for multiple subsequent reads of the bit stream, and track positions of all soft bits detected during the multiple subsequent reads.