Patents Assigned to LSI Logic Corporation
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Patent number: 7434198Abstract: A method of detecting potential failures from a corrected mask design for an integrated circuit includes steps of receiving as input a corrected mask design for an integrated circuit, searching the corrected mask design to find a critical edge of a polygon that is closer than a selected minimum distance from a polygon edge opposite the critical edge, constructing a critical region bounded by the critical edge and the polygon edge opposite the critical edge, comparing the critical region to a potential defect criterion, and generating as output a location of the critical region when the critical region satisfies the potential defect criterion.Type: GrantFiled: December 29, 2005Date of Patent: October 7, 2008Assignee: LSI Logic CorporationInventors: Nadya Strelkova, Santosh Menon
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Publication number: 20080244491Abstract: A method and apparatus are provided for generating and using timing constraints templates for IP cores that can be instantiated in an integrated circuit design. The templates include a plurality of timing constraint statements for inputs and outputs of the respective IP core. At least one of the statements includes a configurable variable, wherein the timing constraints template is configurable through the variable for each of a plurality of instances of the IP core in the integrated circuit design.Type: ApplicationFiled: March 26, 2007Publication date: October 2, 2008Applicant: LSI Logic CorporationInventors: Balaji Ganesan, David Vinke, Ekambaram Balaji, Nicholas A. Oleksinski
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Patent number: 7430700Abstract: The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a method for pausing on a SCAN based test. A second method of the invention provides a method for using stimulations and responses of a known good device to increase fault coverage of patterns in a test flow. A third method of the invention provides a method to curve trace device buffers on an ATE.Type: GrantFiled: February 1, 2007Date of Patent: September 30, 2008Assignee: LSI Logic CorporationInventor: Roger Yacobucci
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Publication number: 20080229045Abstract: In some embodiments, a storage controller comprises a first input/output port that provides an interface to a host computer, a second input/output port that provides an interface a storage device, a processor that receives input/output requests generated by the host computer and, in response to the input/output requests, generates and transmits input/output requests to the storage device, and a memory module communicatively connected to the processor. The memory module comprises logic instructions stored in a computer-readable medium which, when executed by the processor, configure the processor to receive, from the host computer, a write input/output request that identifies a logical volume; compare an amount of storage space available in the logical volume with an amount of storage space required to complete the write operation, and allocate additional storage space to the logical volume if the amount of storage space available in the logical volume is insufficient to complete the write operation.Type: ApplicationFiled: March 16, 2007Publication date: September 18, 2008Applicant: LSI LOGIC CORPORATIONInventor: Yanling Qi
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Patent number: 7409498Abstract: The present invention provides disk coercion by generating coercion percentages or values that can be used to coerce various disks according to each disk's particular labeled size or capacity. In one embodiment, a disk size is received and a base coercion scaling factor is provided such that the received disk size is coerced according to the base coercion scaling factor if the labeled disk capacity is below a disk size threshold. The coercion scaling factor increases for labeled disk capacity above the disk threshold. If the labeled disk capacity is above the disk size threshold, then a coercion scaling factor is provided according to the rate of increase of coercion scaling factors and the labeled disk capacity.Type: GrantFiled: March 2, 2006Date of Patent: August 5, 2008Assignee: LSI Logic CorporationInventors: Brett Henning, Lawrence Rawe, Roy Wade
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Patent number: 7405946Abstract: A pattern of contacts that includes high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in first ordered channels of adjacent transmitter differential pairs. High speed receiver contacts are disposed in a second portion of the pattern, where the first portion of the pattern is not interspersed with the second portion of the pattern, and the high speed receiver contacts are disposed in first ordered channels of adjacent receiver differential pairs. At least one unbroken line of other contacts is disposed between the first portion of the pattern and the second portion of the pattern, where the other contacts do not contain any high speed transmitter contacts and high speed receiver contacts. Low speed IO contacts are disposed in a third portion of the pattern.Type: GrantFiled: May 5, 2005Date of Patent: July 29, 2008Assignee: LSI Logic CorporationInventors: Jeffrey A. Hall, Farshad Ghahghahi
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Patent number: 7405476Abstract: An apparatus includes a first semiconductor die and at least one further semiconductor die. A substrate is attached to the first die and the further die and has an electrical interconnect pattern that interconnects contacts on the first die with respective contacts on the further die. Features of the interconnect pattern have positions on the substrate with smaller tolerances relative to positions of the contacts on the first die than to positions of the contacts on the further die.Type: GrantFiled: October 27, 2005Date of Patent: July 29, 2008Assignee: LSI Logic CorporationInventor: Gary S. Delp
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Publication number: 20080178057Abstract: An improvement to an arithmetic unit of a low-density parity-check decoder, where the arithmetic unit has a pipelined architecture of modules. A first module calculates a difference between absolute values of md_R and md_g_in, and passes the result to a first Gallager module. The first Gallager module converts this value from a p0/p1 representation to a 2*p0?1 representation, and passes the result to a second module. The second module selectively adjusts the result of the previous module based on the sign values of md_g_in and md_R, and passes one of its outputs to a third module (the other two outputs, loc_item_out and hard_out, are not a part of the pipeline). The third module calculates a new md_g value by adding the result of the second module and loc_item_in, and passes this result to a fourth module. The fourth module separates a sign and an absolute value of the new md_g, and passes the result to a second Gallager module.Type: ApplicationFiled: January 24, 2007Publication date: July 24, 2008Applicant: LSI LOGIC CORPORATIONInventors: Alexander Andreev, Vojislav Vukovic, Ranko Scepanovic
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Patent number: 7402770Abstract: A microelectronic switch having a substrate layer, an electrically conductive switching layer formed on the substrate layer, an electrically conductive cavity layer formed on the switching layer, an electrically conductive cap layer formed on the cavity layer, the cap layer forming a first electrode and a second electrode that are physically and electrically separated one from another, and which both at least partially overlie the switching layer, and a cavity disposed between the switching layer and the second electrode, where the switching is layer is flexible to make electrical contact with the second electrode by flexing through the cavity upon selective application of an electrical bias.Type: GrantFiled: November 9, 2005Date of Patent: July 22, 2008Assignee: LSI Logic CorporationInventors: Sey-Shing Sun, Hemanshu D. Bhatt, Peter A. Burke, Richard J. Carter
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Patent number: 7400170Abstract: A differential current-mode driver that meets the IEEE 1394 standard employs a wide output range in common-mode voltage, minimizes timing skew over this wide range, and has well-controlled rise/fall times in the edge rates of the digital signals transmitted, within the window specified by the IEEE 1394 standard, without having to resort to full-swing (VDD to VSS) gate drive signals. In a preferred embodiment PMOS and NPOS transistors are used to provide current for a current driver, in the form of a current steering switch switching a pair of current mirrors. The current mirrors output is input to a predriver waveform circuit which divides current between a data source A and data source B, forming the differential signal pair. Certain key transistors in the current driver are kept in saturation to improve performance.Type: GrantFiled: April 28, 2006Date of Patent: July 15, 2008Assignee: LSI Logic CorporationInventor: Rick Bitting
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Patent number: 7400179Abstract: An apparatus comprising a plurality of flip-flops and a compare circuit. The flip-flops may each be configured to (i) receive a clock signal and an input signal and (ii) generate an output signal. The flip-flops may be configured in series such that the output signal of a first of the flip-flops is presented as the input signal to a second of the flip-flops. The compare circuit may be configured to generate a reset signal in response to each of the output signals. The reset signal is generated until each of the output signals matches a set of predetermined values stored in the compare circuit.Type: GrantFiled: August 29, 2006Date of Patent: July 15, 2008Assignee: LSI Logic CorporationInventor: David H. Lin
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Patent number: 7400543Abstract: A self-timed memory array is disclosed, in which segmentability and metal-programmability are supported while minimizing layout space. Self-timing row decoder circuits are placed at the top and bottom of the array adjacent to respective I/O blocks. A self-timing signal is routed from the top (resp. bottom) of the array to a point halfway down (resp. up) the memory array and then back to a self-timing row decoder at the top (resp. bottom) of the array. The same approach may also be used to account for the bitline wire delay from the bottom (resp. top) of the array to the sense amplifiers in the I/O block. Further flexibility in wire routing is provided by eliminating metal routing layers from unneeded memory cells, and a programmable gate array may be used to allow an arbitrary word size to be chosen for the memory.Type: GrantFiled: November 12, 2003Date of Patent: July 15, 2008Assignee: LSI Logic CorporationInventors: Jeffrey Scott Brown, Chang Jung
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Publication number: 20080168334Abstract: A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B?x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where A is a matrix formed only of permutation sub matrices, B? is a matrix formed only of circulant permutation sub matrices, and D is a matrix of the form D = ( T 0 ? 0 0 0 T ? 0 0 ? ? ? ? ? 0 0 ? T 0 I I ? I I ) where T is a two-diagonal, circulant sub matrix, and I is an identity sub matrix.Type: ApplicationFiled: December 20, 2006Publication date: July 10, 2008Applicant: LSI Logic CorporationInventors: Sergey Gribok, Alexander Andreev, Igor Vikhliantsev
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Patent number: 7397401Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate context information in response to one or more bins on a binary signal. The second circuit may be configured to generate the binary signal in response to (i) one or more input bits on a bitstream signal, and (ii) simultaneously performing in a single cycle (a) an arithmetic decode of the context information and (b) a renormalization of the context information.Type: GrantFiled: July 7, 2006Date of Patent: July 8, 2008Assignee: LSI Logic CorporationInventors: Harminder S. Banwait, Eric C. Pearson, Scott F. James
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Publication number: 20080162070Abstract: The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a method for pausing on a SCAN based test. A second method of the invention provides a method for using stimulations and responses of a slown good device to increase fault coverage of patterns in a test flow. A third method of the invention provides a method to curve trace device buffers on an ATE.Type: ApplicationFiled: December 27, 2007Publication date: July 3, 2008Applicant: LSI LOGIC CORPORATIONInventor: Roger Yacobucci
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Publication number: 20080150090Abstract: A method of forming a metal gate in a wafer. PolySi1-xGex and polysilicon are used to form a tapered groove. Gate oxide, PolySi1-xGex, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi1-xGex, and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolySi1-xGex, and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi1-xGex, and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.Type: ApplicationFiled: January 29, 2008Publication date: June 26, 2008Applicant: LSI LOGIC CORPORATIONInventors: Hong Lin, Wai Lo, Sey-Shing Sun, Richard Carter
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Publication number: 20080155381Abstract: An improvement to a key equation solver block for a BCH decoder, where the key equation solver block having a number of multiplier units specified by X, where: t*(7*t?1)/(codeword_len?3)?X<(t+1), where t is a number of transmission errors for the key equation solver block to correct, and codeword_len is a length of a transmitted codeword to be decoded by the BCH decoder.Type: ApplicationFiled: December 20, 2006Publication date: June 26, 2008Applicant: LSI LOGIC CORPORATIONInventors: Elyar E. Gasanov, Alexander Andreev, Ilya V. Neznanov, Pavel A. Panteleev, Sergei Gashkov
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Publication number: 20080148034Abstract: A multiple-processor system and boot procedure are provided. The system includes an integrated circuit having first and second embedded processors. A volatile memory and a non-volatile memory are shared by the first and second processors. The non-volatile memory includes a set of boot load instructions executable by the first and second processors.Type: ApplicationFiled: December 19, 2006Publication date: June 19, 2008Applicant: LSI Logic CorporationInventors: Russell J. Henry, James K. Sandwell
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Patent number: 7385927Abstract: Methods and structure for standardized communication between a test operator, a host system, and an embedded system under test. Test program instructions are designed, written for, and executed on, an embedded system under test in accordance with standard API functions for message exchange. Still further, the invention provides for standards in the user interface to select a desired test, to start the test with defined parameters and to present reply and status information to the test operator. These user interactions are defined in a test configuration language of the present invention and preferably incorporated with the executable image file to define an integral test vehicle file. The present invention thereby reduces test sequence development time by providing standard API functions for message exchange between a host system test application and the system under test and provides for standardized user interaction in a flexible, easily maintained design language.Type: GrantFiled: June 24, 2002Date of Patent: June 10, 2008Assignee: LSI Logic CorporationInventors: Carl Edward Gygi, Andrew J. Hadley
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Publication number: 20080134008Abstract: An LDPC decoder that implements an iterative message-passing algorithm, where the improvement includes a pipeline architecture such that the decoder accumulates results for row operations during column operations, such that additional time and memory are not required to store results from the row operations beyond that required for the column operations.Type: ApplicationFiled: December 1, 2006Publication date: June 5, 2008Applicant: LSI LOGIC CORPORATIONInventors: Alexander Andreev, Igor Vikhliantsev, Sergey Gribok