Patents Assigned to LSI Logic Corporation
  • Patent number: 7381502
    Abstract: A mask for use in a photolithographic process. The mask includes a plate or substrate having first and second opposite surfaces, a first image on the first surface of the substrate and a second image on the second surface of the substrate. When the mask is used in a photolithographic process, energy is reflected by the first image prior to entering the substrate and energy is reflected by the second image after passing through the substrate.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: June 3, 2008
    Assignee: LSI Logic Corporation
    Inventors: Michael Jay Berman, George Edward Bailey
  • Patent number: 7379422
    Abstract: A networking/communication chip having a receiving buffer or FIFO whereby it receives data from a data source across a network and transfers the data to a host system. The memory in the host system acts as a logical extension of the receiving buffer in the chip; in this way, the host system controls the flow of data from the source, rather than the control flow being based on the capacity of the receiving buffer in the networking/communication chip. The networking/communication chip may be a controller, such as a 10 Gigabit Ethernet controller, wherein data received from the source in one protocol is transformed to a second protocol input to the host. If either or both the networking/communication chip or the host system is/are made of FPGAs, it/they can be reprogrammed to disable the flow control in the networking/communication chip and enable flow control in the host system. Data flow is enhanced because memory in the host system typically is much larger than memory in the networking/communication chip.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: May 27, 2008
    Assignee: LSI Logic Corporation
    Inventor: George Wayne Nation
  • Patent number: 7379416
    Abstract: A method of time division multiplexing for a forward data packet channel includes encoding parallel data sub-packets into parallel streams of turbo codes; interleaving each of the parallel streams of turbo codes to generate parallel streams of quasi-complementary turbo codes; modulating the parallel streams of quasi-complementary turbo codes to generate parallel streams of modulated data symbols; and multiplexing the parallel streams of modulated data symbols by one of multiplexing and non-complete puncturing to generate a single stream of modulation symbols.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: May 27, 2008
    Assignee: LSI Logic Corporation
    Inventors: Hong Kui Yang, Stanislaw Czaja
  • Patent number: 7379281
    Abstract: An electrostatic discharge protection circuit adapted to reduce an electrostatic discharge event on a line of an integrated circuit. The protection circuit includes an NMOS transistor having a source contact that is electrically connected to the line. A drain contact is electrically connected to a logical low voltage, and a gate contact is also electrically connected to the logical low voltage, through a resistor. A substrate bias pump is electrically connected to a back gate of the NMOS transistor, where the bias pump provides a steady state direct current negative bias during normal operation of the integrated circuit when there is no electrostatic discharge event.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: May 27, 2008
    Assignee: LSI Logic Corporation
    Inventors: William M. Loh, Minxuan Liu, Jau-Wen Chen
  • Patent number: 7375570
    Abstract: A circuit which facilitates TDF testing without having to purchase expensive new test equipment, such as a new test platform that is capable of supporting test frequencies well beyond the current 200 MHz limitation. A solution to current TDF testing problems by adding circuitry to the device-under-test (DUT) that is configured to receive two reference clock signals from automated test equipment (ATE), i.e. conventional ATE which does not provide test frequencies beyond 200 Mhz, and create two high-speed clock pulses that serve as the launch and capture clocks for the TDF test sequence on the DUT.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: May 20, 2008
    Assignee: LSI Logic Corporation
    Inventors: Kevin Gearhardt, Doug Feist
  • Patent number: 7376541
    Abstract: A pin-based memory power modeling method using arc-based characterization includes steps as follows. All power arcs of a memory model are identified and characterized. A power arc is selected from the identified and characterized power arcs. Output bus switching power is computed by removing overlapping power using the selected power arc, and a temporary value for various input ramp times and output loads is derived. Output pin power for the selected power arc is calculated using the temporary value and a ratio of a number of output bits switching over an entire bus width. Switching power for the selected power arc is calculated by a power estimation tool based on port activity and an input intrinsic power value.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: May 20, 2008
    Assignee: LSI Logic Corporation
    Inventors: Jia-Lih J. Chen, Naveen Gupta, Ghasi R. Agrawal
  • Patent number: 7376260
    Abstract: A method for performing post-optical proximity correction (OPC) multi layer overlay quality inspection includes the steps of generating a virtual target mask for a first mask and a second mask overlay using design rules at least partially defining the relationship between the first mask and the second mask; creating a composite aerial image representing a first mask image formed from the first mask and a second mask image formed by the second mask by performing imaging of the first mask and the second mask and overlaying the second mask image onto the first mask image; generating an overlay image map of the composite aerial image using the design rules at least partially defining the relationship between the first mask and the second mask; and comparing the overlay image map area and the virtual target mask area.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: May 20, 2008
    Assignee: LSI Logic Corporation
    Inventors: Neal Callan, Nadya Belova
  • Patent number: 7375442
    Abstract: A universal interface circuit and an associated method are provided that can supply a computer logic circuit, such as the components mounted upon an adapter card, with first and second inputs having first and second predetermined voltage levels, respectively, based upon power drawn from both first and second supply voltages. The interface circuit typically includes a first power supply circuit for providing the first input having the first predetermined voltage level in response to the first supply voltage. Additionally, the interface surface includes a regulator for generating an output having the second predetermined voltage level in response to the first supply voltage. The interface circuit further includes a second power supply circuit for providing an output that also has the second predetermined voltage level, albeit in response to the second supply voltage.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: May 20, 2008
    Assignee: LSI Logic Corporation
    Inventors: Charles Clark Jablonski, Stephen Scott Piper, Sukha R. Ghosh
  • Patent number: 7373622
    Abstract: An apparatus including a base layer of a platform application specific integrated circuit (ASIC), a mixed-signal function and a built-in self test (BIST) function. The base layer of the platform ASIC generally includes a plurality of pre-diffused regions disposed around a periphery of the platform ASIC. Each of the pre-diffused regions is generally configured to be metal-programmable. The mixed-signal function may include two or more sub-functions formed with a metal mask set placed over a first number of the plurality of pre-diffused regions. The BIST function may be formed with a metal mask set placed over a second number of the plurality of pre-diffused regions. The BIST function may be configured to test the mixed-signal function and present a digital signal indicating an operating condition of the mixed-signal function.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: May 13, 2008
    Assignee: LSI Logic Corporation
    Inventors: Scott C. Savage, Donald T. McGrath, Robert D. Waldron, Kenneth G. Richardson
  • Patent number: 7371659
    Abstract: A method for forming a feature in a substrate, where residue within the feature can be easily removed. An upper sidewall portion of the feature is formed, where the upper sidewall portion forms a void in the substrate. The upper sidewall portion has an upper sidewall angle. A lower sidewall portion of the feature is formed, where the lower sidewall portion forms a void in the substrate. The lower sidewall portion has a lower sidewall angle. The upper sidewall angle of the upper sidewall portion is shallower than the lower sidewall angle of the lower sidewall portion. By forming the feature with a shallower sidewall angle at the top of the feature, any debris within the feature is more susceptible to rinsing, etching, or other cleaning procedures, and thus the feature is more easily cleaned than standard features having relatively steeper sidewalls.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: May 13, 2008
    Assignee: LSI Logic Corporation
    Inventors: Haruhiko Yamamoto, Hideaki Seto, Nobuyoshi Sato, Kyoko Kuroki
  • Patent number: 7373629
    Abstract: An apparatus comprising an integrated circuit having (i) a number of regions each pre-diffused and configured to be metal-programmed and (ii) a plurality of pins configured to connect the integrated circuit to a socket. A logic portion may be implemented on the integrated circuit (i) configured to implement integrated circuit operations and (ii) having one or more I/O connections and one or more supply connections. A first group of the pre-diffused regions are metal-programmed and coupled to said I/O connections. A second group of the pre-diffused regions are metal-programmed and coupled to the supply connections.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: May 13, 2008
    Assignee: LSI Logic Corporation
    Inventors: Donald T. McGrath, Scott C. Savage, Robert D. Waldron, Kenneth G. Richardson
  • Publication number: 20080109688
    Abstract: A built in self test circuit disposed within a memory matrix. Individual memory cells within the memory matrix are disposed into logical columns. The built in self test circuit has only one memory test controller, which is adapted to initiate test commands and receive test results. Transport controllers are uniquely paired with each one of the logical columns of memory cells. Each of the transport controllers is adapted to receive test commands from the memory test controller, test memory cells within the logical column as instructed by the test commands, receive test results from the logical column of memory cells, and provide the test results to the memory test controller. The transport controllers are also adapted to selectively operate in three different modes under control of the memory test controller.
    Type: Application
    Filed: November 8, 2006
    Publication date: May 8, 2008
    Applicant: LSI LOGIC CORPORATION
    Inventors: Sergey Gribok, Alexander Andreev, Ivan Pavisic
  • Patent number: 7370139
    Abstract: Methods and structures for efficiently storing task file information for a significant number of SATA devices coupled to a SATA storage controller. A RAM memory within the SATA storage controller may store task file information for virtually any number of SATA devices coupled to a SAS communication domain. An arbiter and multiplexing logic is coupled to multiple client logic blocks or processes of the controller each operable to control one or more corresponding SATA devices. The arbiter and associated multiplexing logic grants each client process an opportunity to control its corresponding devices by retrieving saved state information from the task file RAM storage.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: May 6, 2008
    Assignee: LSI Logic Corporation
    Inventors: Patrick R. Bashford, Brian A. Day
  • Patent number: 7369066
    Abstract: A circuit generally including a first module, a second module and a third module is disclosed. The first module may be configured to (i) generate a plurality of parsed residual blocks by parsing a plurality of 4×4 CAVLC (context-based adaptive variable length coding) residual blocks received in an input signal and (ii) generate a plurality of metric signals resulting from the parsing of the 4×4 CAVLC residual blocks. The second module configured to generate a plurality of scanning position signals based on the metric signals. The third module configured to generating an 8×8 CABAC (context-based adaptive binary arithmetic coding) residual block in an output signal by up-sampling the parsed residual blocks based on the scanning position signals.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: May 6, 2008
    Assignee: LSI Logic Corporation
    Inventors: Jamal Benzreba, Harminder Banwait, Eric Pearson
  • Patent number: 7370257
    Abstract: A system and method for collecting and analyzing integrated circuit test vehicle test data by identifying various blocks of circuitry through at least two different intersecting test paths. In one embodiment, the process test circuits may be arranged in a matrix format and connected so that they may be tested along rows or columns. When a failure along a specific row and a specific column is identified, the process test circuit at the intersection may be identified as the failure point.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: May 6, 2008
    Assignee: LSI Logic Corporation
    Inventors: Richard Schultz, Gerald Shipley, Derryl Allman
  • Patent number: 7369743
    Abstract: The present invention is directed to a system, software system and method for effectively managing multimedia broadcast presentations. Effective multimedia broadcast data management offers users increased functionality in how they experience multimedia presentations, manage data and control hardware, such as a personal video recorder. Thus increasing the overall multimedia experience and consequently user satisfaction. Utilization of the present invention allows the user to experience combinations of media previously unavailable. For example, in implementations of the present invention, users may option various combinations of audio and video; including the rate at which a user experiences the media. Further, the user may text search to find starting and stopping points for recording, viewing and pausing operations. Additionally, in embodiments the present invention may be utilized to prioritize stored multimedia presentations.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: May 6, 2008
    Assignee: LSI Logic Corporation
    Inventors: Daniel Watkins, Zhaohui Shen
  • Patent number: 7370309
    Abstract: A method of routing an integrated circuit design includes steps of receiving as input at least a portion of an integrated circuit design including at least two separate routing rules assigned to the same net for routing the integrated circuit design, formulating a single combined routing rule as a function of content of each of the separate routing rules, and generating as output the combined routing rule and a routing rule assignment that assigns the combined routing rule to the net.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: May 6, 2008
    Assignee: LSI Logic Corporation
    Inventor: Alexander Tetelbaum
  • Publication number: 20080102583
    Abstract: A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by the deposition of the gate material in the trench. This process avoids the potential for damage to high-k gate dielectric layers caused by high thermal cycles and also reduces or eliminates the problematic formation of voids in the dielectric layers filling the gaps between adjacent gates.
    Type: Application
    Filed: December 19, 2007
    Publication date: May 1, 2008
    Applicant: LSI LOGIC CORPORATION
    Inventors: David Pritchard, Hemanshu Bhatt, David Price
  • Patent number: 7365015
    Abstract: A method of forming a metal gate in a wafer. PolySi1-xGex and polysilicon are used to form a tapered groove. Gate oxide, PolySi1-xGex, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi1-xGex, and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolyS1-xGex, and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi1-xGex, and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: April 29, 2008
    Assignee: LSI Logic Corporation
    Inventors: Hong Lin, Wai Lo, Sey-Shing Sun, Richard Carter
  • Patent number: 7366862
    Abstract: A method and apparatus are provided for interfacing with a synchronous dynamic memory in which memory commands are provided to the memory. The memory is accessed in response to the memory commands. Read data is captured in a data capture circuit having a delay setting. The delay setting is updated in response to detection of a period of read inactivity of the memory.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: April 29, 2008
    Assignee: LSI Logic Corporation
    Inventors: John M. Nystuen, Steven M. Emerson, Stefan Auracher