Abstract: The amount of data transmitted in a primary data channel is increased by modulating a reference clock signal of the primary data channel with secondary data to form a separate secondary data channel. Primary data is formed into a primary data signal using the modulated reference clock signal, and a transmitter transmits the primary data signal to a receiver. The receiver recovers the primary data and modulated reference clock signal from the primary data signal, and then recovers the secondary data from the recovered modulated reference clock signal.

Abstract: A bridge for connecting a DSP to an ASIC on-chip bus as a slave. The bridge couples signals between a DSP internal memory direct memory interface and an on-chip bus such as the AMBA AHB. The bridge includes a generic slave module which provides direct connections to the on-chip bus in the on-chip bus protocol. It also includes a slave engine connected to the DSP memory interface to control read and write transactions with the memory. The generic slave and the slave engine are coupled by a pulse grower and pulse shaver to allow the engine to operate at DSP clock frequency while the generic slave operates at the usually slower on-chip bus frequency. The bridge allows masters in the ASIC to perform read and write transactions with the DSP internal memory.

Abstract: A mechanism if provided for testing newly-manufactured integrated circuits at the wafer stage. Built-in self-test circuitry is used to test each of the die on a wafer in parallel. Then, when a defect is detected, the die marks itself (e.g., by physically destroying a portion of itself through burnout). The present mechanism eliminates the inefficiencies of serial testing of die and of mechanical latency as each die is positioned for testing.

Abstract: A system for controlling arbitration that may be used for a bus. The system generally comprises a bus, at least one master, and a first circuit coupled between the bus an the at least one master. The at least one master may be configured to present at least one transfer signal. The first circuit may be configured to (i) grant a bus mastership to a first master of the at least one master, (ii) present a first transfer signal of the at least one transfer signal to the bus in response to granting the bus mastership to the first master, (iii) remove the bus mastership from all masters of the at least one master, and (iv) present an idle transfer signal to the bus in response to removing the bus mastership from all masters.

Abstract: A method of increasing mechanical interlocking between a first structure and a second adjacent structure in an integrated circuit. The first structure is formed with a first surface having a first horizontal component, and the second structure is formed with a second surface having a second horizontal component. The first surface laterally engages the second surface and the first horizontal component is complementary to the second horizontal component, such that the first structure prohibits vertical movement of the second structure.

Abstract: A method of finding an optically periodic structure in a cell layer of an integrated circuit design includes receiving as input a physical representation of a cell layer of an integrated circuit design, finding reference coordinates of a selected portion of the cell layer from the physical representation of a cell layer, selecting an initial element located nearest to the reference coordinates, and constructing a base structure that includes the initial element and a minimum number of elements in the physical representation of the cell layer wherein the base structure may be replicated at an X-offset and a Y-offset to fill the entire selected portion so that for each element in each replica of the base structure there is an identical element at identical coordinates in the physical representation of the cell layer.

Abstract: A current amplifier has a variable resistor or capacitor to provide a high frequency boost. Additionally, additional transistors may be switched in and out of the circuit to provide different gains at lower frequency. The combination of variable resistors or capacitors and the switchable transistors provides control over the low frequency gain of the amplifier and the transition region from low gain to higher gain.

Abstract: A method of power sequence protection for a level shifter is disclosed that includes the steps of placing the level shifter in a pre-selected state if an input voltage supply is not powered on when an output voltage supply is powered on and releasing the level shifter from the pre-selected state to follow transitions of an input signal when the input voltage supply is powered on.

Abstract: The present invention is directed to a system and method of providing an embedded input/output interface dynamic load balancing. A method for providing a load balancing function between a host and a target in a network environment by an input/output interface may include providing a logical identifier table by an input/output interface, the logical identifier table including at least one logical identifier, the logical identifier suitable for referencing at least one physical address identifier of a target. Communications are managed between the host and the target by the input/output interface. The communications occurring over at least one of a first route and a second route of at least two routes communicatively coupling the input/output interface to the target are managed so that the host transfers data by balancing data transferred utilizing the second route and the third route of the at least two routes.

Abstract: A longest common subprefix of two binary words p1 and p2 is identified based on bit strings ip1 and ip2 which are extensions of p1 and p2, and binary words n1 and n2 that define the length of p1 and p2. The bit strings and words are processed to set a “greater” output if p1>p2 and to set an “equal” output if p1=p2. A mask having a consecutive string of most significant bits having a first logical value is constructed to identify the matching subprefixes of p1 and p2.

Abstract: Different dynamic range control values are applied to the 2-channel and m-channel outputs without repeating the inverse transform or the windowing of the audio samples. First, m-channel dynamic range control values are applied to audio samples in the frequency domain (“frequency samples” or “frequency coefficients”). The frequency samples are then inverse transformed to generate audio samples in the time domain (“time samples”) and windowed to generate windowed time samples. The windowed time samples are saved and the 2-channel dynamic range control values are applied to the windowed time samples. 2-channel dynamic range control values include 2-channel scale factors that, when multiplied with groups of the windowed time samples, at least partially remove the effects of windowing and the m-ch dynamic range control values applied in the frequency domain and readjust the dynamic range for 2-channel output.

Abstract: The present invention provides a method for forming interconnect lines and conductors and passive devices in the fabrication of an integrated circuit. A gap is created in the patterning of a first layer. The gap is filled by a dielectric material so that an encapsulated conduit is formed in the gap. The encapsulated conduit is filled with a conductor by chemical vapor deposition processes or other deposition processes, the filling facilitated by forming via holes to intersect the conduit, and then filling the via holes. The conductor filled conduit can be used as a resistor, fuse, inductor, or capacitor.

Abstract: Different dynamic range control values are applied to the 2-channel and m-channel outputs without repeating the inverse transform of the audio samples. First, m-channel dynamic range control values are applied to audio samples in the frequency domain (“frequency samples” or “frequency coefficients”). The frequency samples are then inverse transformed to generate audio samples in the time domain (“time samples”). The time samples are duplicated to two sets where the 2-channel dynamic range control values are applied to one set of time samples. 2-channel dynamic range control values include 2-channel final scales that, when multiplied with the first set of time samples, at least partially remove the effects of the m-channel dynamic range control and readjust the dynamic range for 2-channel output. The first set and the second set are then windowed.

Abstract: A method and apparatus for estimating the length of a transmission line is provided. The transmission line extends between a transmitter and a receiver and has a low-pass filter characteristic and an impulse response. The method and apparatus receive a data signal from the transmission line at the receiver and estimate the length of the transmission line as a function of the received data signal and the impulse response.

Abstract: A method for testing integrated circuits, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output from the integrated circuits in response to the predetermined set of input vectors is sensed, and the output from the integrated circuits is recorded in a wafer map, referenced by position designations. The recorded output for the integrated circuits is mathematically manipulated, and the recorded output for each of the integrated circuits is individually compared to the mathematically manipulated recorded output for the integrated circuits. Graded integrated circuits that have output that differs from the mathematically manipulated recorded output for the integrated circuits by more than a given amount are identified, and a classification is recorded in the wafer map for the graded integrated circuits, referenced by the position designations for the graded integrated circuits.

Abstract: An apparatus (22) for reducing noise in a tracking error signal receives input signals from an array (5) of photodetectors, each input signal indicating the amount of laser light incident on the corresponding photodetector reflected from an optical disc. The input signals from diagonal pairs of photodetectors are summed and then filtered and digitized to produce a pair of digital input signals. A signal difference generator (20) produces first and second difference signals when either the first or the second digital input signals are received. The first and second difference signals are received by a programmable timing element having a user programmable device (41) and a signal limiting device (32, 33, 34, 35) for limiting the duration of the first or second difference signals provided at respective first or second outputs of the programmable timing element to a user programmable maximum value.

Abstract: An improved process simulation system for simulating results of fabrication process for a semiconductor device design is disclosed. According to the method and system disclosed herein, the process simulator receives processing parameters and mask data for at least two masks as input, and simulates results of the fabrication process such that an aerial image is generated for each layer of the device that was simulated. After generating the aerial images, the process simulator superimposes the aerial images to create a composite image. An operator is then allowed to misalign at least one of the images in relation to the other images based on one or more offset values. The composite image showing the misalignment is then displayed, allowing the operator to view nominal process capability as well as process fluctuations prior to fabrication of the semiconductor device.

Abstract: A multiple layer mesh design which includes a layer which provides a vertical mesh and an adjacent layer which provides a horizontal mesh which includes an open area or hole. The layer which provides the horizontal mesh (with hole) may either be above or below the vertical mesh layer, depending on the design. The vertical mesh may be full or may surround an open area or hole where the design includes both a horizontal donut mesh and a vertical donut mesh.

Abstract: The present invention is directed to a system and method for parallel configurable IP design. In an aspect of the present invention, a method may include receiving input parameters for a configuration by a common IP development environment. A unique combination of input parameters from the received input parameters is identified. At least one unique runtime file of the common IP development environment is initiated. The unique runtime file is derived from a common set of IP deliverables of the common IP development environment. At least one unique output file from the initiated unique runtime file is generated. The initiated unique runtime file and generated unique output file are unique so as to enable parallel implementation of the configuration specified by the received input parameter with at least one other configuration by the common IP development environment.

Abstract: A method for communicating on a SCSI bus permits out-of-band addressing and communication for normally non-addressable devices such as SCSI expanders and terminators. The method remaps 18 SCSI data lines for out-of-band operation and manipulates no more than those data lines. Some of the data lines are remapped for purposes of out-of-band signaling and data transfers. Advantageously, manipulation of only the SCSI data lines prevents the possible response of a device on the SCSI network that does not support the out-of-band operations. Accordingly, the disclosed method is backward compatible with existing SCSI networks while allowing implementation of devices having the increased functionality of out-of-band communication.