Abstract: An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer.

Abstract: A test vehicle for evaluating a manufacturing process for integrated circuits comprises a staircase of vias and traces arranged for maximum test coverage. The staircase may be combined with several functional cells to produce circuits that exercise many interconnections that may be designed at the minimum design parameters of manufacturing process. The accessibility of many testing methods allows an engineer to quickly find root cause failures and thus make improvements to the manufacturing process.

Abstract: A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

Abstract: The present invention is directed to magnetoresistive memory and data storage devices. A system for providing distributed functionality in an electronic environment includes a plurality of platforms suitable for providing a logic function. The platforms include embedded programmable logic, and MRAM memory, the logic and MRAM memory communicatively coupled via an interconnect.

Abstract: A semiconductor substrate having multiple signal voltage power supplies is provided. The substrate may include a signal voltage power ring separated into segmented voltage supply connections laterally spaced across the upper surface of the substrate. In addition, the substrate may include a voltage supply plane formed within the substrate. The voltage supply plane may be separated into segmented planes. Vias may electrically connect the segmented voltage supply connections to the segmented planes. In an embodiment, at least 2 of the segmented planes may have different voltage supplies. For example, each of the segmented voltage supply connections are configurable to supply power to a portion of input/output drivers of an integrated circuit. Voltage supplies of the segmented planes may be determined based on voltage requirements of the portions of the input/output drivers.

Abstract: The present invention provides a method and apparatus for providing dual-port capability to an SRAM array. The internal nodes of two single-port memory cells are connected to each other through metal-layer programming to form a dual-port memory cell. In a preferred embodiment, a split word line design is used for each single-port memory cell, to facilitate dual-port memory access while minimizing the need for IC layout space. An additional benefit of the present invention is that it allows “slices” of a memory array to be converted into dual-port memory, so as to allow both single-port and dual-port memory cells in the same memory array.

Abstract: A semiconductor device which receives and transmits data at high speed is tested at operational speed at wafer sort. A probe card includes a high-speed interconnect that couples probe output bonding pads to probe input bonding pads. The high-speed interconnect connects a respective output of a transmitter in the die to a respective input of a receiver in the die while the probe card is connected to the die. A built in self test circuit in the die generates test patterns and compares them for accuracy. The test patterns are routed on the high-speed interconnect from the output of the transmitter to the input of the receiver allowing the data path through the receiver and transmitter in the die to be tested at operational speed before the die is assembled into a package.

Abstract: A method of forming an electrical contact on a surface of a substrate. A first layer of a first electrically conductive material is formed on the surface of the substrate, where the first layer is formed in a substantially contiguous sheet across the surface of the substrate. A non electrically conductive masking layer is applied to the first layer, where the masking layer leaves exposed first portions of the first layer and covers second portions of the first layer. The substrate is immersed in a first electrolytic plating bath, and a first electrical potential is applied between the first layer and the first electrolytic plating bath, thereby causing the formation of a second layer of a second electrically conductive material on the exposed first portions of the first layer.

Abstract: A method of forming a metal interconnect in an integrated circuit. A copper layer is formed over dielectric structures on the integrated circuit, where the dielectric structures have an upper level. The copper layer is planarized to be no higher than the upper level of the dielectric structures, without reducing the upper level of the dielectric structures. An electrically conductive capping layer is formed over all of the copper layer, without the capping layer forming over any of the dielectric structures.

Abstract: An improvement to an integrated circuit package substrate of the type that has a bonding ring with an exposed upper surface, where a first portion of the exposed upper surface is for receiving a molding compound and a second portion of the exposed upper surface is for receiving an electrical connection. A solder mask is formed on the first portion of the exposed upper surface of the bonding ring.

Abstract: Embodiments of the invention include a method for forming a copper interconnect having a bi-layer copper barrier layer. The method comprises the steps of providing a substrate in a processing chamber, the substrate having a low-K dielectric insulating layer and an opening in the insulating layer. A first barrier layer of tantalum/tantalum nitride is formed on the insulating layer and in the opening. A second barrier layer is formed on the first barrier layer. The second barrier layer consisting of a material selected from the group of palladium, chromium, tantalum, magnesium, and molybdenum. A copper seed layer is formed on the second barrier layer and a bulk copper layer is formed on the seed layer. The substrate is annealed and subject to further processing which can include planarization.

Abstract: An apparatus and method for using the apparatus for reducing analysis time of integrated circuits. The apparatus includes an integrated logic analyzer inserted in a substrate containing the integrated circuit and means for accelerating circuit analysis using the integrated logic analyzer. The means may be selected from the group consisting of a high speed sampling circuit coupled to the integrated logic analyzer and an on-board circuit testing and analysis apparatus including the integrated logic analyzer. Use of the apparatus enables lower production costs by speeding up circuit analysis as well as providing analysis of high speed circuits in a cost effective manner.

Abstract: A sealing mechanism for a customer replaceable unit (CRU) within a computer system is provided. The sealing mechanism comprises a faceplate for the CRU, wherein insertion and extraction latches are recessed into a trench within that faceplate. The backside of the faceplate has a protruding rim around the perimeter. The rim engages a groove in the subsystem enclosure, which surrounds the aperture that the CRU engages. Since the faceplate incorporates a perimeter ridge and a trench structure, the interacting groove follows the contour of the trench. Thus the rim and groove both trace the faceplate trench around the faceplate. The groove in the subsystem enclosure has an entrenched section at both ends of the receptacle perimeter that accommodate sections of the faceplate rim that trace the trench in the faceplate.

Abstract: A circuit, gate, or device parameter simulation includes data on the initial conditions of manufacture, including illumination conditions on a stepper, material parameters for processing conditions, and chip layout. Optical effects and processing tolerances may be accounted for in the simulation of the final device performance characteristics. The circuit, gate, or device parameter simulation may incorporate optical proximity code software. Simulated active and passive components are generated by the circuit, gate, or device parameter simulation from the simulated patterned layers on the substrate. Feedback may be provided to the circuit, gate, or device parameter simulation to optimize performance.

Abstract: A system and method are disclosed for recording information on a phase change medium is disclosed. The method includes irradiating a region of the phase change medium with a first dose of laser energy. A first portion of the region is irradiated with a second dose of laser energy in a manner that causes the first portion of the region irradiated with the second dose of laser energy to be in a different state than a second portion of the region that is not irradiated by the second dose of laser energy.

Abstract: A method of circuit design for designing integrated circuits with one or more embedded memories. A placement is generated for timing critical logic associated with each included embedded memory in a logic design. An augmented memory boundary is generated for said each included memory. Each augmented memory boundary encompasses one embedded memory and associated said timing critical logic.

Abstract: A the charge pump suitable for use in phase-locked loop (PLL) circuits employed by mixed signal integrated circuits (IC) is disclosed. The PLL charge pump includes a constant current source that generates constant current source references with high power supply rejection for the P- and N-channel devices of the charge pump. Pass-gate transistors are inserted between the output terminals and the drains of the respective P- and N-channel devices. The switching transients power supply and ground are confined to the turn on/off leads of the pass-gate transistors and, thus, are isolated from the constant current source P- and N-channel devices. In exemplary embodiments of the invention, the constant current of the P- and N-channel devices may be made programmable and used for controlling the range of the current controlled oscillator of the PLL circuit.

Abstract: The invention relates to a method and apparatus for vertically scaling a video picture comprising receiving and storing lines of a video frame of a video picture, reading lines of the frame into linestores, applying the lines to a vertical filter and providing an output video line as a function of the lines. Reading the lines of the frame into linestores comprises reading M lines of each successive 2nd line of the frame lines into the linestores. Following generation of the output video line, a further X lines are read from the framestore into the linestores to provide a further set of M lines in the linestores. The M lines are applied to the vertical filter to provide a further output video line as a function of the lines.

Abstract: Channels are acquired and/or searched in a frequency division multiple access (FDMA) wireless system. Initially, a signal that includes a block of FDMA channels is received and filtered so as to select a frequency band that includes the block of FDMA channels. The filtered signal is then processed to obtain measures of certain frequency components in the filtered signal, and a power estimate for at least one of the FDMA channels is calculated based on at least one of frequency component measures.

Abstract: The present invention is directed to a system and method for providing access to semiconductor manufacturing information. The present invention system and method allows users to interface with semiconductor characteristic data and to data associated with manufacturing conditions over a network. The system includes at least one input device for entering manufacturing data. A data storage device capable of storing the database of manufacturing data, including semiconductor characteristic data and manufacturing conditions is networked to the at least one input device. A plurality of remote devices suitable for interfacing with the data are networked to the storage device, such that the manufacturing data is provided to a website for access upon occurrence of failure event.