Abstract: The present invention is directed to a semiconductor structure including a semiconductor substrate having at least one overlying layer formed thereon. The at least one overlying layer including at least one layer of dielectric material. The at least one layer of dielectric material including a protected region having a first dielectric constant and another porous region having a second dielectric constant wherein the value for the second dielectric constant is less than the first dielectric constant. The porous region having been formed by the implantation of a porosity inducing material into the porous region and subsequent annealing. A method for forming such structures is also included.

Abstract: A graded index of refraction optical waveguide is formed in interlayer dielectric material located above a substrate an integrated circuit-like structure. The waveguide includes a refractive layer of optically transmissive material surrounding a core of optically transmissive material within a trench in the dielectric material. The material of the core has a higher index of refraction than the refractive layer and the material of the refractive layer has a higher index of refraction than the dielectric material. More than one refractive layer may also be formed in the trench, with the inner refractive layer having an index of refraction higher than the outer refractive layer and less than the core.

Abstract: A fluted signal pin provides expanded surface area for high frequency operation which minimizes inductive and capacitive effects. The signal pin may be mounted to a circuit board via a support stanchion or membrane during assembly or repair. The membrane may be permanent or removable by heat, water, and/ or detergent. A pin cap optionally is provided to ensure attachment to an overlying integrated circuit package.

Abstract: An apparatus comprising a device and a resistor. The device generally comprises (i) a gate configured to receive an input voltage, (ii) a drain coupled to a first supply voltage, and (iii) a source coupled to an output. The resistive element is generally coupled between the source and a second supply voltage. The apparatus generally provides voltage tolerance between the input voltage and the output.

Abstract: An arrangement for measuring pressure on a semiconductor wafer and an associated method for fabricating a semiconductor wafer are disclosed.

Abstract: A system and method for reading and writing in a multilevel optical data system is disclosed. The system provides control signals for timing acquisition, level calibration, DC control, AGC, equalizer training and data synchronization. The user data is ECC protected and optionally convolutionally encoded before being combined with the control signals in an information block. The multilevel information block can be written to an optical disc as a series of multilevel marks. The optical disc may also contain an Address in Pregroove signal (AIP) to facilitate synchronization during writing of an information block. The AIP signal has an integer number of address frames per information block.

Abstract: An apparatus comprising a method for providing inverting level shifting, comprising the steps of (A) receiving an input signal having a first predetermined voltage level, (B) controlling a voltage level of said input signal and (C) generating an output signal having a second predetermined voltage level, wherein step (C) provides full scale output voltages between a first supply and a second supply.

Abstract: A severable horizontal portion of a fuse link is formed relative to a vertically configured structure in an IC to promote separation of the severable portion upon applying energy from a laser beam. The vertically configured structure may be a reduced vertical thickness of the severable portion, an elevated lower surface of the severable portion above adjoining portions of the fuse link, a protrusion which supports the severable portion at a height greater than a height of the adjoining portions of the fuse link, flowing the melted severable portion down sloped surfaces away from a break point, and a propellent material beneath the severable portion which explodes to ablate the severable portion.

Abstract: A CRC value cache architecture and methods of operation of same to reduce overhead processing associated with managing a CRC value cache memory. The invention first provides for transferring from system memory to CRC value cache memory all CRC values for all sub-blocks of a data block in response to access to a first CRC value for a first sub-block. This reduces overhead processing to arbitrate for control of the system memory for each CRC value for each sub-block of a block. The invention additionally provides that a separate cache table is maintained corresponding to each device within the storage controller that requests CRC values. Each of the multiple cache entry tables is therefore shorter and more rapidly searched as compared to prior techniques thereby further reducing overhead processing to manage the cached CRC values.

Abstract: An interposer card used during qualification tests on integrated circuit packages is disclosed that eliminates the need for sockets and custom boards. The interposer card includes pads for mounting the I/Os of a test package; edge card connectors for connecting the interposer card directly to a test board and for performing bias testing on the test package; and pads for replicating the test package I/Os for connecting the interposer card to an automated electrical testing (ATE) system for performing ATE tests on the test package.

Abstract: The present invention is a bus reset generator capable of asserting a reset upon detection of a desired phase. The bus reset generator may analyze control signals from a bus, and based upon the control signals may determine the current phase of the bus. If the current phase is the desired phase for a reset, then a reset may be asserted. If the current phase is not the desired phase, the bus reset generator may continue to find the desired phase.

Abstract: A precision analog exponentiation circuit includes a precision analog exponentiation circuit includes a first transistor coupled to a reference current for generating a voltage at the first transistor, a second transistor coupled to the first transistor for generating an output current, a variable current source coupled to the first transistor and the second transistor for generating a sum of the reference current and the output current in response to a feedback signal, and a feedback amplifier coupled to the first transistor for generating the feedback signal wherein the variable current source maintains the voltage at the first transistor substantially equal to a reference voltage so that the output current is substantially equal to an exponential function of a control voltage coupled to the first transistor and the second transistor.

Abstract: In a computerized data storage system, snapshot volumes are used to preserve the state of the base volume at various points in time, and later-formed snapshot volumes are retained after rolling back an earlier-formed snapshot volume into the base volume. During the rollback, data writes to the base volume are copied to the later-formed snapshot volumes when necessary to continue to preserve the states of the base volume represented by the later-formed snapshot volumes.

Abstract: A battery charger method and apparatus are disclosed for providing detailed battery status and charging method information for a selected one of multiple batteries that are simultaneously coupled to the battery charger. The battery charger includes a controller. The controller selects one of the batteries to monitor and charge. The controller then starts a measurement cycle for the selected battery. During the measurement cycle, the controller determines current battery characteristics of the selected battery. The controller determines whether the selected battery is ready for charging by determining whether the battery characteristics of the selected battery are within a specified range. If the controller determines that the selected battery is ready for charging, the controller causes the battery charger to start charging the battery. If the controller determines that the selected battery is not ready for charging, the controller selects another battery to monitor and charge.

Abstract: A method and system for automatically calibrating a masking process simulator using a calibration mask and process parameters to produce a calibration pattern on a wafer. A digital image is created of the calibration pattern, and the edges of the pattern are detected. Data defining the calibration mask and the process parameters are input to a process simulator to produce an alim image estimating the calibration pattern that would be produced by the masking process. The alim image and the detected edges of the digital image are then overlaid, and a distance between contours of the pattern in the alim image and the detected edges is measured. One or more mathematical algorithms are used to iteratively change the values of the processing parameters until a set of processing parameter values are found that produces a minimum distance between the contours of the pattern in the alim image and the detected edges.

Abstract: A method implements a change to a circuit design for a system formed on a semiconductor chip, the circuit design including at least one circuit core. The method includes providing in the circuit design at least one field programmable gate array (FPGA) core, extracting an incremental change to the circuit design by comparing a new resister-transfer-level (RTL) design and an old RTL design for the system, synthesizing the incremental change into a netlist for the at least one FPGA core, generating new metal layer interconnections so as to provide an input and an output for the at least one FPGA core in accordance with the incremental change, and programming the at least one FPGA core in accordance with the netlist. The at least one FPGA core is provided in an otherwise unused area of the chip.

Abstract: The present invention is directed to a scale-invariant topology and traffic allocation in multi-node system-on-chip switching fabrics. A method for allocating resources in a design of an integrated circuit may include receiving resource data for components of an integrated circuit. The resource data is suitable for indicating consumption by the components of at least one resource. Integrated circuit resources for the components of the integrated circuit are allocated according to a power law distribution as applied to the received resource data.

Abstract: A photoresist-free and ARC-free lip on the periphery of the upper surface of a semiconductor substrate adjacent the end edge of the substrate is formed by the steps of: forming an ARC layer on one surface of a semiconductor substrate; chemically treating the ARC layer to chemically terminate the ARC layer a first distance from the end edge of the substrate; forming a photoresist layer over the semiconductor substrate and over the ARC layer thereon; and exposing the peripheral portion of the photoresist layer to UV light followed by development of the exposed peripheral portion of the photoresist layer to photolithographically terminate the photoresist layer a second distance from the end edge of the substrate wherein the second distance is smaller than the first distance.

Abstract: A method and system for decoding a biphase-mark input stream is disclosed. Aspects of the present invention include receiving an external biphase-mark input stream by a receiver module; recovering timing information from the input stream; decoding the input stream to generate decoded data and storing the decoded data in a data buffer; reading, by an audio out module, the decoded data from the data buffer at a rate determined by a programmable clock; using the timing information from the receiver module to calculate a sampling frequency of the input stream; and adjusting a frequency of the programmable clock to substantially match the sampling frequency so that the audio out module reads the decoded from the buffer at substantially the same rate that the receiver module inputs the decoded data into the data buffer.

Abstract: A system for monitoring and managing devices on network comprising one or more managed devices connected to the network and storage means for storing a device management application program associated with each of the managed devices. The system further includes a management station which is in communication with each of the managed devices across the network, and the management station is in communication with the storage means. When a user wishes to monitor, configure, or manage one of the managed devices on the network, the user preferably selects the managed device to be managed and the management station retrieves from the storage means the device management application program associated with the selected managed device. By the management station processing the management application program for the selected managed device, the management station allows the user to monitor the status of the managed device, as well as change the configuration of and fix errors with the managed device.