Abstract: Methods and associated structure for saving and restoration of state information regarding progress of an automated test procedure to permit resumption of the automated test procedure following reset or failure of the automated test system. An automated test system in accordance with the present invention preferably saves state information in a non-volatile storage medium, such as a disk file, indicative of the progress of the test procedure. When the test system environment in which the automated test system is operable is reset or restarted, intentionally or due to failure, the automated test system retrieves previously saved state information from the non-volatile storage medium to resume the automated test process in accordance with the saved state information.

Abstract: A chemical vapor deposition process controls the thickness of a film on an edge of a wafer by modifying the density of flow gases at the edge of the wafer through the use of a gas flow control ring. The deposition process is performed with the gas flow control ring disposed about a wafer holding region on a wafer holder. The top surface of the gas flow control ring is controlled relative to the top surface of the wafer to adjust the thickness of the film deposited on the wafer edge. In one particular embodiment, the gas flow control ring has a top surface in the same plane as the top surface of the wafer. In another embodiment, the deposition process is performed with the clearance between the inner diameter of the gas flow control ring and the periphery of the wafer minimized.

Abstract: A method for improving bandwidth utilization in a packet-switched network via real time control of pause frame transmissions. The invention provides a mechanism whereby a pause frame may be effectively negated if, during the transmission of the pause frame, the network conditions necessitating the pause frame are eliminated or abated. In one Ethernet-compliant embodiment of the invention, monitoring circuitry is provided in a network device to ascertain changes in flow control conditions. Following detection of a flow control condition (e.g., a transmit buffer overflow condition), a flow control unit in the network device initiates transmission of a pause frame. Typically, the initial pause time value will be set to a maximum value (e.g., “FFFF”). During or immediately prior to transmission of the pause frame, the monitoring circuitry functions to monitor the state of the flow control unit or flow control enablement signals to determine if the flow control condition remains in effect.

Abstract: A method for determining an end point of a planarization process for removing metal from a surface of a substrate submerged in an electrolytic solution or slurry. A first electrode is provided which is operable to contact the surface of the substrate, such as a working electrode of a potentiostat system. A second electrode is provided which is operable to contact the electrolytic solution, such as a reference electrode of the potentiostat system. The first electrode is contacted to the surface of the substrate and an electrochemical property is measured, such as the electrochemical potential between the first and second electrodes, where the electrochemical property is indicative of an electrochemical characteristic of the substrate-slurry system. The planarization process is preferably stopped when a substantial change in the electrochemical potential of the system is measured.

Abstract: An array controller of a data storage system initiates a test of another array controller of the data storage system to determine the operational condition of the controller under test (CUT) as well as an array of storage devices to which the CUT is connected and a network fabric over which the CUT receives commands from host devices of the data storage system. If the CUT or devices connected thereto are not functioning properly, the controller initiating the test can diagnose the problem. The controller initiating the test instructs the CUT to perform certain normal operating functions, e.g. data read and write functions, and checks whether the functions are completed correctly. Additionally, a loopback test checks the operation of the network fabric, and the read and write functions also check the operation of the storage devices.

Abstract: A platen for use in a dry etching process for substrate production, the platen having a surface susceptible to chipping and/or particle generation from the dry etching process and a coating applied to at least a portion of the surface for rendering the surface less susceptible to chipping and/or particle generation, the coating comprising a silicon carbide coating.

Abstract: A plurality of devices communicate information over a wireless network at radio frequencies. The information includes digital audio, video and data. Bandwidth among the devices is dynamically allocated, the allocation being based upon the needs of the devices. One embodiment of the wireless network is a Time Division Multiple Access network. Another embodiment is a wireless Ethernet. Yet another embodiment is a Frequency Division Multiplexed network.

Abstract: The present invention is directed to a method and system for automating data storage array components testing. A serial number of a data storage array component (i.e., product) is used to determine if the product is of high priority (rank) in comparison with other products in a queue and there is any test cell available for testing the product. Next, if a test is required, the product type and test requirements of the product are retrieved from a database based on the serial number, and the product is routed to the test cell from an assembly line. Then the product and a storage component interface module of the test cell are positioned so that the product and the storage component interface module face each other. The storage component interface module is chosen based on the test requirements retrieved from the database. Next the product is docked into the storage component interface so that the product is connected to the storage component interface module. Then the test is run to completion.

Abstract: A partially manufactured semiconductor chip comprising a slice and a number of shells is a template for a communication and networking chip. The slice has a number of I/O ports, blocks, and PHYs. The hardmac PHYs are established to correspond to a high speed data transmission protocol. The interior of the template comprises logic gate arrays and configurable memory. Once particular protocols of data receipt and transmission are selected, the logic gate arrays and configurable memory can be programmed and otherwise configured to develop protocol layers for data networking and communication.

Abstract: A vortex unit suitable for providing a desired environment for a semiconductor process may include a vortex tube and a semiconductor processing device suitable for performing a semiconductor processing function. The vortex tube includes an air inlet for receiving compressed air, a first air exhaust for outputting an air stream having a temperature greater than the received compressed air, and a second air exhaust for outputting an air stream having a temperature lower than the received compressed air. The semiconductor processing device is connected to the second air exhaust of the vortex tube so that the semiconductor processing device receives a cooled air stream from the vortex tube, the cooled air stream providing an environment suitable for enabling the semiconductor processing device to perform the semiconductor processing function.

Abstract: The present invention is directed to a method of recovering a write ahead log after an interruption. In a first aspect of the present invention, a method of writing a log entry of a write ahead log may include initiating a log write to a write ahead log, the write ahead log having a first sector, and a second sector, wherein the first sector is followed by the second sector. A log entry including a sequence number is written to the second sector. Then, the log entry including the sequence number is written to the first sector.

Abstract: A method, program and system for recovering data from a failed drive in a RAID system are provided. The invention comprises assigning a plurality of storage drives within the RAID to a defined volume group. If a failure of a drive in the volume group is detected, the failed drive is removed from the volume group, and data from the failed drive is redistributed to the drives remaining in the volume group. In another embodiment of the present invention, a previously unused drive in the RAID is assigned to the volume group to replace the failed drive, and the data on the failed drive is reconstructed on the newly assigned drive. In yet another embodiment, two or more previously unused drives are assigned to the volume group to replace each failed drive. The data from the failed drive is then re-striped across the remaining drives in the volume group, including the newly assigned drives.

Abstract: An oscillator circuit includes an electrical load, a first metal oxide semiconductor (MOS) devise, a second MOS device, and a negative feedback circuit. The electrical load is coupled between a first node and a second node. The first MOS device is coupled between the first node and a third node, and controls a first current flowing from the first node to the third node. The second MOS device is coupled between the second node and a fourth node, and controls a second current flowing from the second node to the fourth node. A positive feedback circuit is formed with the first and second MOS devices. The positive feedback circuit has inputs from the first and second nodes and outputs to the first and second MOS devices. The negative feedback circuit has inputs from the third and fourth nodes and outs to the first and second MOS devices.

Abstract: The present invention is directed to a system and method for disabling and recreating a snapshot volume. A method of disabling repository volume activity corresponding to a point-in-time image and retaining repository volume attributes may include initiating a command in a electronic data storage system. The command disables copy-on-write activity to a repository volume created in relation to a first point-in-time image of a base volume, in which repository volume attributes are retained suitable for providing a repository volume corresponding to a second point-in-time image. A method of creating a point-in-time image of a base volume may include initiating a command to create a second point-in-time image of a base volume. The second point-in-time image is created utilizing a repository volume having attributes retained from a repository volume created previously with respect to a first point-in-time image.

Abstract: The present invention provides a comprehensive design environment defining a system architecture and methodology that may integrate interconnects, cores, ePLC, re-configurable processors and software into a manageable and predictable system designs that achieve on-time system IC design results meeting desired specifications and budgets. For example, an interscalable interconnect maybe provided that is scalable and isochronous capable. Additionally, an abstract language may be provided to be able to describe interconnecting core functions. Further, a self-progrmnmable chip may be provided that, upon receiving a construct, it could program itself to achieve the desired functionality, such as through the use of on-chip knowledge and the like.

Abstract: A method for fabricating buried channel NMOS devices and the devices themselves are disclosed. These buried channel NMOS devices are fabricated with a p-type substrate, an n-type implant in the top portion (approximately 400 to 1000 Å deep) of the substrate, and an insulating gate dielectric above the n-type implant. An n-type or p-type doped polysilicon gate electrode is formed on top of the insulating gate dielectric. The n-type implant region is doped in such a way that it is depleted of charge carriers when the device's gate electrode is at the same potential as the well (zero bias). When the gate electrode is biased +Ve with respect to the device's well substrate a conducting channel of mobile electrons is formed in a portion of the buried layer. This type of biasing is known as inversion bias since the charge carriers are of the opposite type than the p-well.

Abstract: An integrated circuit test apparatus and a method for testing an integrated circuit are described. The integrated circuit test apparatus includes a holder adapted to receive a wafer, where a frontside of the wafer is accessible to be probe tested by electrically conducting probe needles during which a backside of the wafer is accessible to be scanned by an optical scanning mechanism. The scanning mechanism can optically detect photoemission-generated defects resulting from electrical stimuli applied to the integrated circuits via the probe needles. The holder is coupled to a three-dimensional translational mechanism that will allow for automated multi-die test probing.

Abstract: A method and apparatus for transmitting data in a node having a buffer. A first set of data is received in a buffer for transmission to a target node. The first set of data is sent to the target node. Responsive to an indication that the target node is unable to receive data, a second set of data is loaded into the buffer for transmission to another target node, while the first set of data is retained in the buffer.

Abstract: The present invention concerns an apparatus comprising a first plurality of contacts, a second plurality of contacts, one or more sockets, and a programmable processor. The first plurality of contacts may be configured to receive one or more first signals. The second plurality of contacts may be configured to present one or more second signals in response to the one or more first signals. The one or more sockets may be configured to receive one or more third signals from one or more programmable devices. The programmable processor may be configured to generate a test signal in response to (i) the one or more first signals and (ii) the one or more third signals.

Abstract: A method is provided for fabricating an integrated circuit having a logical function. The method includes fabricating first and second routing layer masks and a first via mask. The first routing layer mask includes power supply segments and signal segments. The second routing layer mask includes signal segments and filler segments, wherein the filler segments are located in unused areas of the second routing layer mask. The first via mask defines vias that electrically couple the filler segments to the power supply segments. If the logical function is changed after the masks have been fabricated, a second via mask is fabricated. The second via mask decouples a filler segment from the power supply segments and couples the filler segment to a signal segment defined by the first routing layer mask to implement the logical function change. The integrated circuit is then fabricated with the first and second routing layer masks and the second via mask.