Abstract: A circuit for reducing the number of bits in a K bit value from K to N bits. The circuit generally comprises a first summing circuit, a control circuit, an error feedback circuit, a second summing circuit, and a processor. The first summing circuit may add an error offset value and the N+m MSB's of the K bit value to produce a result data value. The control circuit may generate a dither offset value. The error feedback circuit may receive m LSBs of the result data value and generate an error value in dependence on the m LSBs. The second summing circuit may add the dither offset value and the error value to provide the error offset value. The processor may selectively control generation of the dither offset value and the error value.

Abstract: Provided are a self-aligned semiconductor fuse structure, a method of making such a fuse structure, and apparatuses incorporating such a fuse structure. The fuse break point, that point at which the electrical link of which the fuse is part is severed by a laser beam, is self-aligned by the use of photolithographically patterned anti-reflective dielectric coatings. The self-alignment allows the size location of the break point to be less sensitive to the laser beam size and alignment. This has several advantages including allowing photolithographic control and effective size reduction of the laser spot irradiating the fuse material and surrounding structure. This permits reduced fuse pitch, increasing density and the efficiency of use of chip area, and results in reduced thermal exposure, which causes less damage to chip. In addition, laser alignment is less critical and therefore less timely, which increases throughput in fabrication.

Abstract: A process for inhibiting the passage of dopant from a gate electrode into a thin gate oxide comprises nitridation of the upper surface of the thin gate oxide, prior to formation of the gate electrode over the gate oxide, to thereby form a barrier of nitrogen atoms in the upper surface region of the gate oxide adjacent the interface between the gate oxide and the gate electrode to inhibit passage of dopant atoms from the gate electrode into the thin gate oxide during annealing of the structure. In one embodiment, a selective portion of silicon oxide on a silicon substrate may be etched to thin the oxide to the desired thickness using a nitrogen plasma with a bias applied to the silicon substrate. Nitridation of the surface of the etched silicon oxide is then carried out in the same apparatus by removing the bias from the silicon substrate.

Abstract: A polishing table 11 in the CMP apparatus 10 has a diameter smaller than the diameter of a polishing pad 12. The polishing pad 12 is disposed on the polishing table so as to cover the entire top surface of the polishing table 11. A space 13 is formed between outside of the outer peripheral surface of the polishing table 11 and under the outer peripheral bottom surface portion of the polishing pad 12 projecting outside from the edge of the polishing table 11. A trough 14 with an opening 14a on top thereof as a device for withdrawing the used slurry is disposed around the outer peripheral surface of the polishing table 11 so as to be located a part thereof in the space 13.

Abstract: A method for detecting contaminants on an implement. A stream of gas is directed over at least a portion of the implement, to entrain at least a portion of the contaminants on the implement, and produce a contaminant laden stream of gas. At least a portion of the contaminant laden stream of gas is sampled, and the amount of contaminants in the sampled portion of the contaminant laden stream of gas is measured. The amount of contaminants in the sampled portion of the contaminant laden stream of gas is reported.

Abstract: An on-chip data independent method and apparatus for channel error estimation in a data recovery scheme is based on measuring phase noise statistics. The apparatus (10) receives a data pulse and four quadrature clock signals and has a discriminating device (11) to provide a count signal for each data pulse received depending on which clock signal was the first to clock the particular data pulse. A pair of counters (12 and 13) counts the number of data pulses received at different phase offsets to provide a value representing a statistical ratio of the counts at different clock phase offsets from which an error rate for the received data pulses based on the counts at different clock phase offsets can be determined from a look-up table (16). By re-configuring the circuitry, the system can be adapted to measure clock window asymmetry.

Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates.

Abstract: A circuit configured to correct a duty cycle error or vary the duty cycle of a clock signal. The circuit includes a differential amplifier or control circuit that receives differential signal inputs. At least one differential pair of transistors is connected to outputs of the differential amplifier or control circuit. Outputs of the one or more differential pairs of transistors are connected to inputs of a differential circuit. The differential amplifier or control circuit is connected to the outputs of the differential circuit. The one or more differential pairs of transistors is configured to change a DC level of at least one of the inputs of the differential circuit in order to shift a cross over point of the inputs of the differential circuit and thereby effect a duty cycle change (or correction) at the outputs of the differential circuit.

Abstract: In digital processing, a method and circuit for implementing at least one of a maximum and a minimum instruction between a source operand and a destination operand in which an arithmetic operation is performed using the source and destination operands to generate a result and the storage of data in a destination storage is controlled in accordance with the sign of the source operand, the sign of the destination operand and the sign of the said result.

Abstract: An apparatus and method is disclosed which enables a host computer to adjust the caching strategy used for writing its write request data to storage media during execution of various software applications. The method includes the step of generating a caching-flushing parameter in the host computer. The cache flushing parameter is then transferred from the host computer to a controller which has a cache memory. Thereafter, a quantity of write request data is written from the cache memory to a storage medium in accordance with the cache-flushing parameter.

Abstract: The invention is directed to optimization of an initial routing that connects nets on a surface, each of the nets including plural interconnected net pins. The surface is divided into a set of areas, and a boundary pin is defined at each point on a boundary of one of the areas where the boundary of the one of the areas intersects a net. Routing optimization is then performed in at least one of the areas, the routing optimization optimizing the routing among the net pins and the boundary pins within the at least one of the areas. The invention is also directed to optimization of an initial routing that connects nets on a surface, each of the nets including plural interconnected net pins. The surface is divided into a first set of pre-defined areas, and routing optimization is performed independently in each of the pre-defined areas in the first set.

Abstract: A test coupon for performing pre-qualification test on a substrate is disclosed. The test coupon includes at least two substrate test structures, and an edge connector for providing external electrical connections. Traces patterned on the test coupon connect the test structures with the edge connector, such that a test apparatus maybe coupled to the edge connector for testing the test coupon without the need to manually solder connections to the test coupon. The test coupon may also be used to perform the actual qualification of certain process changes in substrate construction and to monitor production lot quality and reliability.

Abstract: A metastability risk simulation analysis device and method for identifying metastability risks of a design. The metastability risk simulation analysis device includes computer readable code which is configured to analyze simulation information relating to the design and determine whether the design presents a metastability risk. Desirably, the computer readable code is configured to determine whether two signals, such as a data signal and a clock signal of a synchronous element of the design, cross over each other thereby presenting a metastability risk, and is configured to generate a summary report identifying those synchronous elements of the design which present a metastability risk.

Abstract: An E-beam generator and detector arrangement sends an electron beam through a series of differentially evacuated vacuum chambers of small size to detect faulty circuitry in individual semiconductor devices. The vacuum chambers are open to one end and are sealed by the semiconductor device without contacting the vacuum chambers. A laser generator is operated by a control system with the E-beam generator and detector arrangement to provide a laser beam in a known physical relationship to the electron beam to correct detected faulty circuitry in the semiconductor devices. The E-beam generator and detector arrangement confirms the correction without further handling of the semiconductor device.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: A method of making a ball grid array package includes the steps of (a) laying out an even I/O pad row and an odd I/O pad row of m I/O pads each for a ball grid array package wherein m is a positive integer, (b) laying out an even via row of m+1 vias directly below each odd I/O pad row, and (c) laying out an odd via row of m−1 vias directly below each even I/O pad row. A ball grid array package includes an even I/O pad row and an odd I/O pad row of m I/O pads each wherein m is a positive integer, an even via row of m+1 vias directly below each odd I/O pad row, and an odd via row of m−1 vias directly below each even I/O pad row.

Abstract: In order to descramble sections of scrambled data interleaved with sections of unscrambled data in a transport stream of broadcast video data, while leaving the sections with the original timing relationship in the transport stream, a common data flow path (1-5) is provided both for sections of scrambled data and sections of unscrambled data and signal path loops (6,7; 8,9) including cipher means (62,64) to enable the descrambling of scrambled data, and a control state machine for controlling the flow of data through said common data flow path and said signal path loops to enable passage of unscrambled data sections and descrambling of scrambled data sections, while maintaining the desired relative positions of the data sections.

Abstract: According to the present invention, a first plurality of solder bumps are arranged the active surface of an integrated circuit die in the form of a grid comprising a plurality of rows and a plurality of columns, where the plurality of rows are parallel to two opposing edges of the active surface and the plurality of columns are perpendicular to the plurality of rows. The plurality of columns are separated by a distance D. Each of the solder bumps in every other row is separated from an adjacent solder bump in that row by a distance 2D such that the each of these solder bumps is disposed along a first group of the plurality of columns. Each of the solder bumps in the remaining rows, is separated from an adjacent solder bump in that row by the distance 2D such that the solder bumps in the remaining rows are disposed along a second group of the plurality of columns. Each column within the second group of columns is adjacent to, and in between, two of the columns within the first group of columns.

Abstract: An apparatus for detecting a predetermined pattern of bits in a data bitstream includes a series of detecting elements (2-6), each detecting element in the series corresponding to a predetermined bit in the predetermined pattern. Each detecting element receives a data bit from the data bitstream (8), the corresponding predetermined bit in the predetermined pattern and an error signal from a previous detecting element in the series. The output of each detecting element is an error signal indicative of the number of mismatches between the data bit and the corresponding predetermined bit in the predetermined pattern, both in previous detecting elements in the series in previous clock cycles and in the current detecting element in the current clock cycle. The error signal of the final detecting element (6) of the series is coupled to a logic control element (18) for detecting that a maximum allowed level of mismatches has been detected.

Abstract: A double data rate (DDR) circuit for testing of a high speed DDR interface using single clock edge triggered tester data. The DDR testing circuit includes a first register, a second register, and a multiplexer (MUX). A clock signal is fed to the first register and the MUX. The inverse of the clock signal is fed to the second register. A tester data signal is fed to the first register which generates a latched tester data signal which is fed to the MUX. The inverse of the latched tester data signal is fed to the second register which generates a transformed tester data signal which is fed to the MUX. The MUX generates a combination of the latched tester data signal and the transformed tester data signal for transmission as an applied test data signal. The resulting applied test data signal has double the data rate of the tester data signal upon which it is based.