Abstract: An apparatus comprising a plurality of register logic circuits, a core circuit, a memory circuit, and a plurality of logic circuits. The register logic circuits may each be configured to generate a first logic signal in response to (i) an input data signal, (ii) a second logic signal, (iii) a first clock signal and (iv) a second clock signal. The core circuit may be configured to generate a plurality of data signals and a first control signal in response to the first logic signals and a second control signal. The memory may be configured to present the second control signal to the core circuit. The logic circuits may each be configured to present the second logic signal in response to the first logic signal and the data signals. An embedded FPGA core may be enabled to provide an interconnect to a chip. Additionally, software may enable a wide variety of features including bug fixes and product variations, all without changing the silicon.

Abstract: A method and apparatus for accommodating irregular memory write word widths allow for writing to multiple rows in a memory so as to reduce or eliminate holes in the address read space. First and second memory blocks are provided that include a first bitcell selectable by a first write bitline and a second bitcell selectable by a second write bitline. Where a write word width is not equal to a read word width and is not some factor of a power of two times the read word width, the column decode to read out the entire word is not a power of two, and holes in the read address space will exist. When the write address is even, a first range of bits is written to the first block on a first write bitline, a second range of bits is written to the second block on the first write bitline, and a third range of bits is written to the first block on a second write bitline.

Abstract: An mixer includes a differential signal input, a differential local oscillator input, a gain control input and a differential signal output. The mixer has a stepped signal gain from the differential signal input to the differential signal output which is variable from a first gain to a second, different gain as a function of the gain control input and has a substantially constant DC common mode output bias voltage at the differential signal output.

Abstract: A method and apparatus for synchronization of an audio/visual bitstream is transmitted by an encoder and received by a decoder by employing duplication or elimination of audio samples and video pixels. The invention enables clock synchronization between the encoder and a decoder with an unregulated clock oscillator so as to control the data reader by skipping ahead (eliminating a data element) or to pause (duplicating a data element) depending on whether the encoder clock is faster or slower than the decoder clock.

Abstract: In a multi-directional orthogonal frequency division modulation (OFDM) communication system, for example, on a digital subscriber line, an uplink channel is provided by a first group of the OFDM sub-channels (sub-carriers), and a downlink channel is provided by a second group of the OFDM sub-channels (sub-carriers). In one aspect, communication efficiency is improved by controlling the relative number of sub-channels allocated to each group, and hence controlling the capacity of the channels dynamically. Preferably, the relative capacities are controlled in response to demand for channel capacity. In another aspect, the orthogonality of the sub-carriers generated by different transmitters is improved by providing a frequency and/or time synchronizing signal for providing reference frequency and timing.

Abstract: A cell scheduling and forwarding technique for an input-buffered N×N non-blocking crossbar switch which provides worst-case intra-switch port cell forwarding service delays which are bounded by the duration of N cell forwarding timeslots. This scheduler is further enhanced to support efficient rate based forwarding service.

Abstract: Provided is an interposer tape which provides electrical communication between a die and a packaging substrate. The dimensions of the interposer tape may vary to accommodate a variety of die sizes for the same packaging substrate. The interposer tape includes an array of traces. A first set of wire bonds is formed between the array of traces and the die. A second set of wire bonds is formed between the array of traces and the packaging substrate.

Abstract: A multilevel clock tree uses a temporary clock buffer or reference signal in a clock tree deskew circuit to dynamically minimize skew in a variable delay clock signal that synchronizes operation of synchronized circuit components of an integrated circuit. There are multiple temporary clock buffer signals at each level of the multilevel clock tree. Skew between the temporary clock buffer signals are minimized by providing identical path lengths and path geometries at each level of the temporary clock buffer. The clock tree deskew circuit reduces the clock tree skew, on a level by level basis, in repeated intervals over a period of time. When each level of the tree deskew circuit is deskewed, that level of the clock tree deskew circuit is then turned off to prevent unnecessary further adjustments to the clock signals, but can be turned back on when conditions change that alter the clock tree skew.

Abstract: An improved method and apparatus for transferring data in a CD-ROM system. The CD-ROM system includes a buffer manager for identifying the capacity of a buffer memory used to store data from a disc. The buffer manager controls the transfer of data into and out of the buffer memory. Each time a sector of data is transferred from a disc into the buffer memory, a counter is incremented to track the amount of data in the buffer memory. If the counter equals the capacity of the buffer memory, the transfer of data from the disc is halted. Further transfer of data is not allowed until buffer memory is available.

Abstract: A digital audio decoder is described. The digital audio decoder includes: (i) an audio core which defines a hardware for sub-band synthesis and windowing during decoding of MPEG and AC-3 digital audio signals; (ii) an input RAM coupled to the audio core and configured to store discrete samples in preparation for the sub-band synthesis and the windowing and configured to store intermediate values that are calculated by the audio core during the sub-band synthesis and written back to the input RAM. A process of decoding MPEG and AC-3 digital audio signals is also described.

Abstract: According to the present invention, a method for creating a package for a semiconductor die, the package comprising a flexible tape, comprises the following steps. A support with an opening has a plurality of arms extending through at a portion of the opening. For example, for a square opening, there may be eight arms, two extending from each side of the opening. The arms preferably form a “z” shape or some other shape with a transverse component. The flexible tape is then attached to the ends of the arms within the opening such that the flexible tape is supported by the arms. A die is attached to the flexible tape, the die is preferably covered with a molding compound, and the die/flexible tape assembly is scribed from the support, thereby creating an individual package.

Abstract: An interconnection system having a bottom metal layer that has a conduction layer with a sidewall and an overlying barrier layer. A lateral barrier layer is disposed adjacent the sidewall of the conduction layer, and an insulation layer is over the bottom metal layer. The insulation layer forms vias extending through the insulation layer to the bottom metal layer. A top metal layer extends through the vias to electrically contact the bottom metal layer. The overlying barrier layer and the lateral barrier layer are relatively resistant to interaction with the top metal layer as compared to the conduction layer.

Abstract: Disclosed is a pupil aperture, and method for making the pupil aperture for use in a photolithography scanner system. The pupil aperture includes a plate having a set of pole apertures that are radially offset from a reference center point of the plate. The plate further includes a horizontal reference line that intersects the reference center point. The horizontal reference line is used to define a target angle that is between about 15 degrees and about 35 degrees from the horizontal reference line. The target angle defines an off-axis location for each of the set of pole apertures. In a specific aspect of this invention, a set ranging between 3 to 9 pole apertures can be defined in the plate, and their offset from the center point can be selected to be between about 0.3 inches and about 0.9 inches.

Abstract: An apparatus for receiving and processing an electrical signal in the form of a pulse train comprising a plurality of pulses. The apparatus generally comprises a processor, a memory and a timer. The timer may be configured to generate a respective value representative of the positions of each leading and trailing edge of each pulse in the pulse train. The memory may be configured to receive the value and write the value. The timer may be configured to generate an interrupt signal following receipt of the trailing edge of the last pulse in the pulse train and apply the interrupt signal to the processor. The processor may read the values stored in the memory for decoding the pulse train in response to said interrupt signal.

Abstract: A method of performing data shifts in a data processing system between a source and a plurality of destinations using a direct memory accessing scheme, comprising the steps of: (A) reading a data block from the source destinations; (B) writing the data block to a first of the plurality of destinations; and (C) writing the data block to a second of the plurality of destinations. Addresses of the first and second destinations are previously stored.

Abstract: A video decoder decimates an input image to produce a decimated output image. The video decoder uses approximately every line of pixels in the input image to compute the lines of pixels in the decimated image. The video decoder includes a vertical decimation filter that computes an average, and preferably a weighted average, of luminance (luma) values associated with pixels from each of four lines in the input image. The decimation filter preferably computes a weighted average of lumas from four adjacent lines of pixels from the input image which may represent a frame or a field of video data. The weighted average preferably uses coefficients that weight each luma in the calculation differently. After calculating all of the luma values for a particular line of the decimated image, the line number associated with the first of the four adjacent lines is incremented by four (in a field-based system) to determine the initial line number for calculating the next line in the decimated image.

Abstract: A process for fabricating a trench filled with an insulating material in a surface of an integrated circuit substrate is described. One step of the process includes defining a masking layer on a composite layered stack above a region to be protected on the integrated circuit substrate surface. The composite layered stack includes a layer of a first material and a polishing stopping layer. The layer of the first material has a polishing rate by chemical mechanical polishing that is greater than a polishing rate by chemical mechanical polishing of the insulating material. Another step of the process includes etching through the composite layered stack and the integrated circuit substrate to form the trench in the integrated circuit substrate surface and depositing the insulating material on the integrated circuit substrate surface such that the trench is filled with the insulating material.

Abstract: A process is disclosed for forming low k dielectric material between and over a plurality of spaced apart metal lines previously formed over a dielectric layer of an integrated circuit structure. The steps include: depositing, over and between the plurality of metal lines, a layer of a first low k dielectric material resistant to via poisoning; then planarizing the layer of first low k dielectric material sufficiently to open voids formed in. the first low k dielectric material between the metal lines; then depositing, over the layer of first low k dielectric material and into the opened voids, a layer of second low k dielectric material capable of filling the opened voids in the layer of first low k dielectric material; and then depositing a layer of a third low k dielectric material resistant to via poisoning over the first low k dielectric material and the voids filled with the second low k dielectric material.

Abstract: A capping layer of an insulator such as silicon oxynitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines is then deposited over and between the metal lines and over the silicon oxynitride caps on the metal lines. After the formation of such void-free low k silicon oxide dielectric material between the closely spaced apart metal lines and the silicon oxynitride caps thereon, the structure is planarized to bring the level of the low k silicon oxide dielectric material down to the level of the tops of the silicon oxynitride caps on the metal lines. A further layer of standard k silicon oxide dielectric material is then formed over the planarized void-free low k silicon oxide dielectric layer and the silicon oxynitride caps.

Abstract: There is disclosed a digital processor having an arithmetic unit and a zero detection circuit and a method of performing zero detection in a digital processor in which a zero detection circuit is connected to the input of the arithmetic unit rather than being connected to the output thereof as is conventional. This enables testing the input to the arithmetic unit independently of the arithmetic unit itself so as to detect when the output value from the arithmetic unit is zero. The result is to take the delay of the zero detection circuit out of the critical processing path.