Abstract: A method of generating a back-annotated standard delay format file for designing integrated circuits with conditional/moded delays is disclosed that includes the steps of receiving as inputs a main input file, a conditional delay specifications file, and a selected option switch; inserting delay information from the conditional delay specifications file for each cell entry in the main input file according to the selected option switch into an output data structure; and generating the back-annotated standard delay format file from the output data structure.

Abstract: A linear assignment problem for an ordered system containing a plurality of boxes each containing an object having an associated penalty function is solved. A hierarchy contains a bottom level containing at least as many generalized boxes as there are boxes in the assignment problem, and top and intermediate levels. The objects of the assignment problem are placed in the generalized box of the top level. A first local task is executed to transition the contents of a generalized box of a higher level to at least two generalized boxes of the next lower level. A second local task is executed on the generalized boxes of the lower level to minimize a global penalty function. The first and second tasks are executed through successive iterations until all of the objects are placed in the generalized boxes in the bottom level in a layout having minimal penalty function.

Abstract: A method of planarizing a wafer surface of a semiconductor wafer having an elevated portion extending therefrom is described. The method includes the step of positioning a fluid flow surface relative to the wafer surface so that (i) a space is defined between the wafer surface and the fluid flow surface, and (ii) the elevated portion of the semiconductor wafer is positioned in the space. The method also includes the step of advancing a fluid within the space so that the fluid contacts and erodes the elevated portion of the semiconductor wafer. An associated apparatus for planarizing a wafer surface of a semiconductor wafer having an elevated portion extending therefrom is also described.

Abstract: A decoder for decoding convolutionally encoded precoding data is described. The precoding sequence consists of two subsequences t and b; the value of t corresponds to a convolutional encoder state at a particular time. The a priori probability Pr(ti) that the subsequence t has a particular value ti is generated. In the preferred embodiment, the metric function that is applied to a test sequence including ti is then biased by adding (&sgr;2/&agr;2) ln(Pr(ti)), where &agr;2 is the signal average energy per symbol of the transmitted data, &sgr;2 is the variance of the noise added by a channel through which the data is transmitted. The resulting metric is then used by an MLSE decoder such as a Viterbi decoder to decode the received data.

Abstract: A BGA package wherein power is provided to the die through power (Vdd) balls which are located in an inner most row of solder balls. By arranging the power balls in an inner most row, it is possible to reduce the distance the electrical signal has to travel to reach a power ring. Preferably, ground is provided to the die through ground (Vss) balls which are dispersed in a ball field around the periphery of the inner most row of power balls. Preferably, the ground balls are paired together, because by pairing the ground balls, it is possible to use only one via for two ground balls on the system board. This reduces the number of layers needed on the system board to route all of the pins and may make it possible, for example, to route more traces on the system board.

Abstract: A method for preparing at least one metal layer of an integrated circuit for visual analysis. The at least one metal layer to be visually analyzed is exposed, and a solution of nitric acid, acetic acid, and ammonium fluoride is applied to the at least one metal layer. The at least one metal layer is rinsed to substantially remove the solution, and the s integrated circuit is dried. The solution is made with one part nitric acid, three parts acetic acid, and two parts ammonium fluoride. The nitric acid is a solution of about seventy percent by weight in water, the acetic acid is glacial acetic acid, and the ammonium fluoride is a solution of about forty percent by weight in water. The solution is at a temperature of about seventy degrees Fahrenheit, and is applied to the at least one metal layer by swabbing the solution onto the layer for between about ten seconds and about fifteen seconds. The step of exposing the at least one metal layer includes sawing the integrated circuit along a desired cross section.

Abstract: A method and apparatus are provided for analyzing test vectors for use in measuring static current consumed by an integrated circuit. A netlist of interconnected cells is read to identify cell types used within the netlist, wherein the netlist includes a plurality of nodes. Once the netlist has been read, cell characteristics for selected ones of the cell types are read from a technology library to identify pins of the selected cell types to be monitored. The nodes in the netlist that correspond to these pins are identified and are added to an list file. Once the list file has been generated, a computer simulation program is used to simulate a steady-state response of a functional model of the integrated circuit to a potential test vector and to output the resulting logic states on the nodes provided in the list file.

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands.

Abstract: Provided is a non-destructive method of detecting die crack problems in an integrated circuit. The method provides for testing for die crack problems in all chips and in many production chips without adding any extra circuitry or pads. In a preferred embodiment, the method takes advantage of an existing NAND gate tree structure at the perimeter of many conventional dies, although the invention is also applicable to other logic gate structures that may exist or may be formed at the perimeter of dies. The invention recognizes that this NAND gate tree structure may be used in order to identify and localize die cracks in finished chips, thereby providing a faster, more accurate and nondestructive way to test for die cracks in production chips. A typical NAND gate tree structure has the form of a cascade inverter chain. Since one end of the first NAND gate is tied to VDD, the output of each gate will alternate between low and high.

Abstract: A method of pin placement for an integrated circuit includes the steps of (a) receiving as input a corresponding set of pin constraints for each pin of a hard macro, (b) receiving as input a specification for the hard macro, (c) locating pin slots on each side of the hard macro, (d) finding at least one of a horizontal interval and a vertical interval on a side of the hard macro for each pin of the hard macro, and (e) assigning each pin of the hard macro to a pin slot within the horizontal interval and the vertical interval that satisfies the corresponding set of pin constraints.

Abstract: A receiver for detecting a stream of optical data bits which are transmitted at a predetermined frequency includes a plurality of optically-active devices arranged on an integrated circuit substrate in an array. The plurality of optically-active devices are capable of being positioned to receive the stream of optical data bits which are transmitted as light, and each of the optically active devices is capable of detecting light in an optically active state and generating a detected signal corresponding thereto. A control circuit receives a clock signal at a rate corresponding to the predetermined frequency and generates control signals which cause a different one of the plurality of optically-active devices to be in the optically active state during each successive period and thereby detect the presence of light during each of said successive periods and generate the detected signals corresponding to the data bit stream.

Abstract: When a mobile communication unit (e.g. a cellular telephone) is powered up, the unit must lock on to a local base station, or “acquire” a base station signal, to enable the user to send and receive calls. To lock on a local base station, the mobile unit must determine the delay at which the base station is sending the pseudo random (PN) code. This process is called the “acquisition.” The current art of acquiring a base station involves collecting a set of samples at a particular code phase, or delay, testing the collected sample, and repeating these steps using another code phase until the correct code phase is found. The present invention discloses a method and apparatus for collecting a set of samples at a particular code phase, and simultaneously testing the collected sample and collecting the next set of samples for another code phase.

Abstract: Forward error correction apparatus and methods are described. A forward error correction system includes multiplier for computing an erasure location polynomial. An erasure location is applied to an input of a input register. An output of a given register in a series of registers and an output of the input register are multiplied to produce a product. The product and an output of the dummy register are added to produce a sum. The sum is applied to an input of a subsequent register immediately following the given register. The subsequent register is treated as the given register and the above-described steps are repeated for each of the erasure locations. A two-buffer method and apparatus for computing an error location polynomial using the Berlekamp error correction algorithm also is described.

Abstract: A method for assigning signal traces to one of a plurality of power planes on a power layer of an integrated circuit package. The integrated circuit package has an integrated circuit signal contact region, a top routing layer, and a bottom routing layer. The power layer underlies both the top routing layer and the bottom routing layer. First signal traces on the bottom routing layer are routed from contacts disposed in a core portion of the integrated circuit signal contact region to first ball contacts disposed within a first perimeter of the integrated circuit package. The first perimeter has dimension corresponding to a first distance from the integrated circuit signal contact region. Second signal traces on the top routing layer are routed from contacts disposed in a peripheral portion of the integrated circuit signal contact region to second ball contacts.

Abstract: In order to optimise power consumption, an electronic circuit assembly comprises clock means for switching a plurality of gate circuits, the gate circuits including a first gate circuit having a first power consumption as a function of clock frequency, and a second gate circuit performing a similar function as the first circuit and having a second power requirement as a function of frequency, and means for switching off one gate circuit and switching on the other gate circuit in dependence upon the intended frequency of operation. The circuit assembly may be an arithmetical operation circuit or a finite state machine.

Abstract: Methods for designing an integrated circuit is disclosed. In the present invention, the integrated circuit is first created by placing and routing standard cells of the integrated circuit. After routing the standard cells, empty spaces unused by the standard cells are extracted. After extracting the unused areas, clusters of metal-programmable transistors are inserted into the unused areas by an area-based placement/routing tool to form “ponds” of gates (POGs). When design changes are desired after the formation of the integrated circuit, the metal-programmable transistors are programmed to form desired spare cells to implement the desired design changes by making changes to the upper layer masks for the integrated circuit.

Abstract: The present invention has application to final balancing of an initial balanced clock tree. In one aspect of the invention, a minimum set of clock buffer delays is generated to reduce clock skew to within a selected skew limit for each level of a balanced clock tree. In one embodiment, the difference between the optimum delay and the clock buffer delay selected from the minimum set of clock buffer delays for each clock buffer in the balanced clock tree is less than or equal to the selected skew limit.

Abstract: A method for making a flip chip ball grid array (BGA) package includes the step of thinning a die for matching a composite coefficient of thermal expansion to that of a second level board.

Abstract: Relevant logic cells and waveforms of a circuit are automatically identified, traced and displayed by using conventional simulation, schematic viewing and waveform viewing tools. The input and output waveforms to and from each logic cell and a transition and a transition time point of each waveform are derived. The output waveform and a selected transition time point identify a predictive input waveform and its transition time, which cause the output signal transition at the selected transition time point. The predictive input signal is the output signal of a preceding, predictive logic cell, thereby identifying the preceding predictive logic cell. Repetitions of this procedure are performed with each new identified predictive logic cell to automatically derive a series or logic cone of cells.

Abstract: An integrated circuit includes a vertical-interdigitated capacitor located between an upper interconnect layer and a lower interconnect layer. Both interconnect layers include conductors formed of a metal capable of atom diffusion or ion migration, such as copper. The capacitor plates contact an interconnect layer conductor to create barrier layers to prevent atom diffusion or ion migration from the conductors at the contact locations. Additional barrier layers contact the conductors at locations other than where the capacitor plate portions contact the conductors, and the additional barrier layers are preferably formed of the same material and at the same time that one of the plates is formed. The integrated circuit may include a via plug interconnect extending between conductors of upper and lower interconnect layers, with a plug barrier layer surrounding the plug material to prevent atom diffusion or ion migration from the plug material.