Abstract: A method for wafer bumping includes the steps of spreading a layer of an electrically conductive paste on a surface having a plurality of electrical contacts and exposing a beam-paste interaction volume to a beam of energy to bond a portion of the layer of the electrically conductive paste to at least one of the plurality of electrical contacts for forming a wafer bump.

Abstract: A current-mode peak detector circuit is disclosed. The current-mode peak detector circuit includes an input transistor for receiving an input current that impresses a voltage on a control node, a pair of transistors for providing an output current in response to the voltage at the control node, and a decay control circuit for controlling the decay of the voltage at the control node such that the output current is representative of a peak value of the input current signal. A clamp circuit may be provided for clamping the input voltage to a predetermined level. All of the elements of the current-mode peak detector circuit may be realized using transistors for facilitating integration of the current-mode peak detector circuit on an integrated circuit. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other researcher to quickly ascertain the subject matter of the technical disclosure.

Abstract: An architecture for a low power, high density (smaller area) asynchronous memory comprises memory cells including a forward inverter and a feedback inverter disposed in a back-to-back arrangement (i.e., back-to-back inverters), two write access transistors, a read inverter, and a read access transistor. The architecture employs a double ended write into the memory cells wherein Write Bit Lines coupled to write access transistors are precharged to Vdd−Vtn, or, alternately Vdd, when the signal Write Enable (WE) is low (i.e., “0”).

Abstract: A video decoder is provided with robust error handling and concealment. In one embodiment, the video decoder detects syntactic, semantic, and coding errors in encoded slices of macroblocks. An error handler determines the number of remaining un-decoded macroblocks in the corrupted slice and replaces these corrupted macroblocks using substitute DCT coefficient matrices and motion vectors. The zero-frequency DCT coefficient of each substitute matrix is set equal to the zero-frequency DCT coefficient of the last uncorrupted macroblock, while the higher frequency DCT coefficients are set equal to zero. The substitute motion vectors are provided from a concealment vector memory which buffers the motion vectors of the previous macroblock row. In this way, intelligent approximations are made for the missing macroblocks, effectively masking the video bitstream error.

Abstract: A transmission system for transmitting a signal from a host to a transmission medium is disclosed. The transmission system includes a current-mode digital-analog converter, an on-chip low-pass filter, a line driver, and output impedance control. Further, a method for transmitting a signal from a host to a transmission medium using on-chip filtering is disclosed. More specifically, an apparatus and method for providing precise control of the filter cut-off frequency at high frequencies is disclosed. The transmission system and method can be used in transmission of Ethernet signals onto an unshielded twisted pair cable. In addition, with appropriate modification, the transmission system and method can be used for transmitting ATM or other signals onto a transmission medium.

Abstract: A method of altering topology of a serial bus having a plurality of nodes interconnected in a tree topology in order to increase data rates between the plurality of nodes includes the step of obtaining a current topology representation of the serial bus which indicates a first node of the plurality of nodes is coupled to a second node of the plurality of nodes via a third node of the plurality of nodes. Another step of the method includes obtaining data rate capabilities of each node of the serial bus. The method further includes determining based upon the current topology representation of the serial bus and the data rate capabilities of each node that the third node of supports a third maximum data rate that is slower than a first maximum data rate supported by the first node and a second maximum data rate supported by the second node.

Abstract: A method and apparatus dissipates heat generated by an electronic device. The apparatus includes a channel structure that is in thermal communication with heat generated by the electronic device. The apparatus further includes a pump array operative to advance fluid within the channel structure. In addition, the apparatus includes a baffle array positionable in relation to the channel structure in a first group position and a second group position, wherein fluid advancing within the channel structure is diverted to flow (i) in a first flow path defined in the channel structure when the baffle array is positioned in the first group position, and (ii) in a second flow path defined in the channel structure when the baffle array is positioned in the second group position.

Abstract: An integrated circuit device including a semiconductor die and optical signal emitting diodes for communicating different color optical signals, such as multi-phase clock or trigger signals, to individual circuits on the die. Each circuit includes a filter to discriminate the desired frequency and a photosensitive active device implemented on the die for converting the received optical signal to an electronic signal for clocking or triggering a local circuit (e.g., a data storage register). Translucent material encapsulates the emitter diode and the die. The optically communicated signal has very low skew, which is independent of the topology of the die.

Abstract: An apparatus (22) for reducing noise in a tracking error signal receives input signals from an array (5) of photodetectors, each input signal indicating the amount of laser light incident on the corresponding photodetector reflected from an optical disc. The input signals from diagonal pairs of photodetectors are summed and then filtered and digitized to produce a pair of digital input signals. A signal difference generator (20) produces first and second difference signals when either the first or the second digital input signals are received. The first and second difference signals are received by a programmable timing element having a user programmable device (41) and a signal limiting device (32, 33, 34, 35) for limiting the duration of the first or second difference signals provided at respective first or second outputs of the programmable timing element to a user programmable maximum value.

Abstract: A method of conditional branching in a pipelined processor. The method comprising the steps of (A) prefetching a branch target address in response to encountering a branch instruction, in prediction of taking a branch, and (B) evaluating between (i) taking the branch and (ii) not taking the branch substantially contemporaneously with prefetching the branch target address.

Abstract: A semiconductor package is disclosed. According to one embodiment, the package comprises a substrate having a top surface with traces thereon and a bottom surface with solder balls thereon, the substrate comprising at least three material layers defining at least four substantially planar metal layers, wherein one of the metal layers comprises a reference layer that serves as a reference to both traces on a metal layer above the reference layer and traces on a metal layer below the reference layer. A semiconductor die is mounted to the substrate and bonding wires electrically connect the semiconductor die to the traces on the top surface of the substrate. The traces on the top surface of the substrate are electrically connect to the solder balls through vias and possibly through routing on another metal layer.

Abstract: A distributed computer aided design (CAD) system includes a CAD server station and one or more CAD client stations remote from the server station but connectable thereto via a communications medium such as an intranet or the internet. The CAD server station includes a CAD tool for performing CAD tasks and a communications interface. The CAD client stations include display and data entry facilities for displaying a design parameter entry document to a user and for accepting design parameters entered by the user, as well as a communications interface for transmitting entered design parameters via the communications medium to the server station. The CAD tool at the server station is configured to receive the design parameters from the client station, to perform CAD tasks based on the design parameters and to return processed design data to the server station via the communications medium. The client station can include a workstation with a web browser capability.

Abstract: An apparatus for mounting a heat sink to a chip package such as a BGA type chip package or the like is disclosed. In an exemplary embodiment, ground bumps are formed on the die substrate of the chip package and on the heat mating surface of the heat sink to be attached to the package. The ground bumps formed on the die protrude into the body of dimples formed in the body of the chip encapsulation package to make thermal/electrical ground contact with the ground bumps formed on the heat mating surface of the heat sink for electrically grounding the heat sink.

Abstract: A method and apparatus for generating a Fiber Channel compliant frame when a user enters a simple test pattern. A system is provided in which a user can enter an unencoded user test pattern for a Fiber Channel link which is being tested. The system then can then determine and combine additional information that will format the user's unencoded test pattern into a Fiber Channel compliant frame. The user can then visualize on a display the established Fiber Channel compliant frame and decide whether to modify the Fiber Channel compliant frame before outputting it to the link under test. A comparison can be performed between the data stream that is received after a transmission to the Fiber Channel link to determine whether the Fiber Channel link is in compliance with an established standard.

Abstract: The present invention is a method for cleaning the cavities in electronic components by providing a semiconductor component having an outside surface and a cavity therein. The component including hole in the outside surface enabling fluid flow in to or out of the cavity. The component is immersed in a solvent bath where solvent is flowed into the cavity using the hole, the solvent cleaning the cavity and then optionally being evacuated from the cavity. Specifically, the principles of the present invention may be used to clean the underfill space of a flip-chip package. The flip-chip package includes a packaging substrate with an evacuation port passing through the bulk of the packaging substrate such that the port is in communication with the underfill space and a bottom surface with the packaging substrate. This assembly is immersed in a solvent filled solvent bath. Solvent is drawn into the underfill space through said port. Alternatively, solvent may be injected into the underfill space through the port.

Abstract: A process-is disclosed for planarizing an integrated circuit structure by chemical mechanical polishing (CMP) after filling, with at least one metal, a plurality of trenches and/or vias formed in a silicon oxide layer on the integrated circuit structure. The process, which is capable of inhibiting formation of concave surface portions on the silicon oxide surface, during the CMP process, in regions where said trenches and/or vias are closely spaced apart, comprises forming, over a layer of silicon oxide of an integrated circuit structure, an antireflective coating (ARC) layer of dielectric material capable of functioning as a stop layer in a CMP process to remove metal; and using this ARC layer as a stop layer to assist in removal of excess metal used to fill trenches and/or vias formed in the oxide layer. The particular material chosen for the ARC layer should have a lower etch rate, in a CMP process to remove metal, than does the underlying oxide dielectric layer.

Abstract: A composite layer of low k silicon oxide dielectric material is formed on an oxide layer of an integrated circuit structure on a semiconductor substrate having closely spaced apart metal lines thereon. The composite layer of low k silicon oxide dielectric material exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines, deposition rates in other regions comparable to standard k silicon oxide, and reduced via poisoning characteristics. The composite layer of low k silicon oxide dielectric material is formed by depositing, in high aspect ratio regions between closely spaced apart metal lines, a first layer of low k silicon oxide dielectric material exhibiting void-free deposition properties until the resulting deposition of low k silicon oxide dielectric material reaches the level of the top of the metal lines on the oxide layer.

Abstract: The slew rate of a digital logic output signal delivered from an output pad of an integrated circuit is controlled relative to a load connected to the output pad. At least two pluralities of trigger signals at sequentially spaced time intervals are generated, and the time intervals between the first and second trigger signals or the temporal occurrence of the first and second trigger signals in relation to the load connected to the output pad is selected to change the slew rate of the output signal. The timing of the plurality of trigger signals is established in relation to an input signal to which the driver circuit responds and in relation to the change in the output signal with time as influenced by the load connected to the output pad.

Abstract: A connector and pin structure for coupling with a higher density, finer conductor pitch ribbon cable or the like is disclosed. The connector has an array of pins disposed thereon where a beveled tip of the pin allows for the pin to penetrate the insulation sheath of a corresponding conductor, and the pins have a contacting structure that facilitates contact between the pin and the conductor. In one embodiment, such as where the conductor comprises a braided conductor, each pin has a bulge structure that allows for optimal contact between the pin and the conductor. In another embodiment, such as where the conductor comprises a braided conductor or a solid wire conductor, the pin is asymmetrical and has a notch structure that allows for optimal contact between the pin and the conductor.

Abstract: A horizontal deflecting optical waveguide is formed in an integrated circuit-like structure having a substrate and at least one layer of dielectric material above the substrate. A trench is formed in the dielectric material, and the trench has first and second portions angularly joined at a bent portion. A reflective layer of material adjoins, conforms to and extends along the side walls of the trench. A core of optically transmissive material conforms to the reflective layer within the trench. The reflective layer forms a wall at the bent portion which reflects light from the core located in one portion into the core located in the other portion.