Patents Assigned to LSI Logic
  • Patent number: 6346488
    Abstract: A film of low k dielectric material formed on a semiconductor substrate is treated to inhibit cracking of the film of low k dielectric material during subsequent exposure of the film of low k dielectric material to elevated temperatures by implanting the film of low k dielectric material with hydrogen ions by applying a negative DC bias to the semiconductor substrate in the presence of a plasma of hydrogen ions. The semiconductor substrate is mounted on an electrically conductive substrate support in a reactor and the negative DC bias is applied to the semiconductor substrate by connecting the electrically conductive substrate support to a source of negative DC bias while hydrogen ions are generated by the plasma in the reactor to thereby cause the hydrogen ions to implant into the film of low k dielectric material on the semiconductor substrate.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: February 12, 2002
    Assignee: LSI Logic Corporation
    Inventor: Alex Kabansky
  • Patent number: 6347291
    Abstract: A system for precisely locating an absolute position of a target structure disposed at a known relative position on a substrate, where the substrate has devices in a pattern. Input means receive information, including a substrate size, a pattern offset, a device size, the known relative position of the target structure, and a target structure shape. Staging means receive the substrate in a known orientation. Processing means are used to locate several positions. A center position of the substrate is located from the substrate size and the known orientation of the substrate. A first intermediate position is located by combining the center position of the substrate with the pattern offset. A second intermediate position is located by combining the first intermediate position with at least a first component of the device size. A third intermediate position is located by combining the second intermediate position with the known relative position of the target structure.
    Type: Grant
    Filed: January 5, 2000
    Date of Patent: February 12, 2002
    Assignee: LSI Logic Corporation
    Inventor: Michael J. Berman
  • Patent number: 6346490
    Abstract: Damaged surfaces of a low k carbon-containing silicon oxide dielectric material are treated with one or more carbon-containing gases, and in the absence of an oxidizing agent, to inhibit subsequent formation of silicon-hydroxyl bonds when the damaged surfaces of the low k dielectric material are thereafter exposed to moisture. The carbon-containing gas treatment of the invention is carried out after the step of oxidizing or “ashing” the resist mask to remove the mask, but prior to exposure of the damaged surfaces of the low k dielectric material to moisture. Optionally, the carbon-containing gas treatment may also be carried out after the initial step of etching the low k carbon-containing silicon oxide dielectric material to form vias or contact openings as well, particularly when exposure of the damaged surfaces of the low k dielectric material to moisture after the via etching step and prior to the resist removing oxidation step is possible.
    Type: Grant
    Filed: April 5, 2000
    Date of Patent: February 12, 2002
    Assignee: LSI Logic Corporation
    Inventors: Wilbur G. Catabay, Wei-Jen Hsia, Alex Kabansky
  • Patent number: 6346676
    Abstract: An electrical cable suitable for transmission of data signals cable includes a dual layer ribbon cable with a first layer being offset from the other layer by an offset distance. The dual layer ribbon construction of the cable allows the cable to be compliant with a SCSI standard and to include a VHDCI compliant connector. The cable may have a first Z form where a spacer connects an insulator in the first layer with an insulator in the second layer, a second form in which an insulator of the first layer is attached to an insulator in the second layer, or a modified second form in which a spacer is attached between adjacent insulators in the same layer. The double layer ribbon cable construction allows the width of the cable to be reduced to accommodate a smaller pitched, larger pin number VHDCI compliant connector anywhere along the length of the cable.
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: February 12, 2002
    Assignee: LSI Logic Corporation
    Inventor: Barry Caldwell
  • Patent number: 6343519
    Abstract: An apparatus detects the approach and touch-down of an object relative to a sensor panel. The apparatus includes a digital filter for determining a first derivative of a current flow in the sensor panel and a controller determines when the first derivative reaches a maximum. In a preferred embodiment, a magnitude for current flow in a plurality of corners of the sensor panel is determined by the controller. These magnitudes are then summed to determine a current flow from which the first derivative is computed. The current flow is analyzed by the controller to determine when an object is approaching the sensor panel, has contacted the sensor panel, and is withdrawn from the sensor panel. Thresholds are used to avoid false detection of approaching objects.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: February 5, 2002
    Assignee: LSI Logic Corporation
    Inventors: Steven P. Callicott, Billy B. Duncan, William K. Petty, Mark S. Snyder
  • Patent number: 6345378
    Abstract: A practical approach for synthesis for million gate ASICs is based on the use of synthesis shells. The synthesis shell is generated by beginning with a gate level description of a fully characterized and optimized block. This gate level description is reduced by removing internal gates to produce a synthesis shell of the synthesized block. The synthesis shell preserves input load and fanout for the block, output delay relative to clock for the block, setup/hold constraints on input signals relative to the clock for the block, and delay from input to output for pass through signals for the block. Such a synthesis shell can be used as a substitute for original design netlists and can be used for hierarchical synthesis in a customer's design environment, or as a deliverable from a provider of ASIC services in order to protect the intellectual property of such a provider.
    Type: Grant
    Filed: March 23, 1995
    Date of Patent: February 5, 2002
    Assignee: LSI Logic Corporation
    Inventors: Christian Joly, Zarir Sarkari, Ravichandran Ramachandran, Sarika Agrawal, Sanjay Adkar
  • Patent number: 6345368
    Abstract: A network comprises at least one host processing system, a number of storage controllers, each coupled to one of a plurality of storage arrays, each storage array including at least one mass storage device. Each storage controller may be couple to at least one host processing system and to at least one other storage controller to control access of the host processing systems to the mass storage devices. Multiple copies of data are maintained in storage arrays that are geographically remote to each other, such that any copy can be accessed by any host. Each storage controller includes an interface with a host that emulates a mass storage device and an interface with a local storage array that emulates a host. The interfaces to the host and local storage arrays are independent of the type of host or devices in the local storage array. Two or more hosts may be dissimilar to each other, and two or more storage arrays may include dissimilar mass storage devices. Hosts access stored data using virtual addressing.
    Type: Grant
    Filed: January 15, 1999
    Date of Patent: February 5, 2002
    Assignee: LSI Logic Corporation
    Inventor: James R. Bergsten
  • Patent number: 6342734
    Abstract: A metal-insulator-metal capacitor is formed between interconnect layers of an integrated circuit with one of the plates of the capacitor formed integrally with one of the interconnect layers. A dielectric layer is formed on top of the interconnect layer, and a top capacitor plate is formed thereon. A bottom plate is defined by the interconnect layer and extends laterally beyond the top plate so that via interconnects may connect to both plates. An intermetal dielectric (IMD) layer separates the interconnect layer and the capacitor from the next interconnect layer above, and the via interconnects are formed through the IMD layer to connect the above interconnect layer to the capacitor plates. The dielectric layer on top of the interconnect layer that defines the bottom plate and another dielectric layer formed on top of the top plate may serve as etch stops for forming the vias for the via interconnects to different levels.
    Type: Grant
    Filed: April 27, 2000
    Date of Patent: January 29, 2002
    Assignee: LSI Logic Corporation
    Inventors: Derryl D. J. Allman, John Q. Walker, Verne C. Hornback, Todd A. Randazzo
  • Patent number: 6342803
    Abstract: The present invention includes a pad driver circuit that has a driver, a power-on circuit coupled to the driver and a power-off circuit coupled to the driver. The power-on circuit is coupled to a pad via the power-off circuit. The power-on circuit provides a high impedance path between the pad and a power supply, particularly when the power supply is off. The power-off circuit provides a stepped-down voltage to the driver when the voltage signal is received. The driver is an open drain driver that includes series pull-down devices. The pad driver further includes a second power off circuit coupled to the driver. The power-on circuit provides a power supply voltage to the driver when a power supply is on. The power-on device preferably includes an inverter coupled to receive a power supply voltage and a clamp coupled to receive an output of the inverter wherein the clamp provides a voltage responsive to the power supply voltage.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: January 29, 2002
    Assignee: LSI Logic Corporation
    Inventor: Michael J. McManus
  • Patent number: 6342429
    Abstract: Provided is a technique for forming an indium field implant at the bottom of an STI trench to strengthen the p-well under field oxide, but to not weaken the n-well under the field oxide. The diffusivity of indium is an order of magnitude smaller than that of boron and the activation level of indium is high enough for well dopings. Thus, the implanted indium is able to keep the concentration of p-dopant at the p-n well junction under the field isolation and the oxide/silicon interface high, even with boron depletion, so that punchthrough is avoided.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: January 29, 2002
    Assignee: LSI Logic Corporation
    Inventors: Helmut Puchner, Shih-Fen Huang
  • Patent number: 6341198
    Abstract: A memory buffer allowing preliminary access to an upstream data portion in a data stream and a method for allowing the access. This memory buffer is a “peek-ahead” FIFO comprising a data input that receives a data stream, a data output, a circular FIFO buffer that stores data from the input at a circulating read location and provided data from a circulating write location to the data output. The memory buffer also has read and write pointers that indicate the read and write locations in the FIFO buffer. If the upstream data portion is stored in the memory buffer, the read pointer can temporarily advance by an offset number of memory locations to allow reading of the upstream data portion. In one embodiment, this memory buffer is included in a DVD decoder and is used to identify the type of an incoming packet before the entire header of the packet is processed. Also described is a method and system for parsing data words from an interleaved byte stream.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: January 22, 2002
    Assignee: LSI Logic Corporation
    Inventors: Todd C. Mendenhall, Manabu Gouzu
  • Patent number: 6341142
    Abstract: A serial data transceiver is presented which includes elements which facilitate testing using only the serial data transfer terminals of the transceiver. The serial data transceiver includes a transmitter and a receiver. The transmitter receives parallel data, converts the parallel data to a serial data stream, and transmits the serial data stream. The receiver receives a serial data stream, converts the serial data stream to parallel data, and provides the parallel data. During testing, parallel data produced by the receiver is routed to the transmitter input. In one embodiment, the transmitter includes a first router for routing parallel input data to the transmitter, and the receiver includes a second router for routing parallel output data produced by the receiver. The first router is coupled to the second router, both routers receive a test signal.
    Type: Grant
    Filed: December 16, 1997
    Date of Patent: January 22, 2002
    Assignee: LSI Logic Corporation
    Inventors: Francois Ducaroir, Karl S. Nakamura, Michael O. Jenkins
  • Patent number: 6341092
    Abstract: A system and method are presented for incorporating boundary scan test capability in an embedded memory. Existing half-latches within the memory are augmented to create full-latches, configurable as a scan register. This requires substantially less circuitry than if the entire scan register was created separately. Furthermore, separate signal paths are maintained for the functional signals and for the boundary scan data. Therefore, the boundary scan logic does not contribute additional propagation delay to the functional signals. Also, because the test circuitry is within the memory (rather than external to it), placing and routing of the scan circuitry is much less complicated than with previous methods.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: January 22, 2002
    Assignee: LSI Logic Corporation
    Inventor: Ghasi R. Agrawal
  • Patent number: 6341355
    Abstract: Upon receiving a normal select signal to switch from one clock to another the first clock continues as the output for a number of clock periods. The normal select signal is treated as a disconnect control signal only at the next positive edge of the first clock. The disconnect signal is delayed for a number of cycles and then applied to the control gate of the first clock only when a negative edge of the first clock is detected. Once the disconnect control signal has been issued and the first clock output is dead, the disconnect control signal starts the sequence for connecting the second clock to the output. The connect control signal is accepted at the next positive edge of the second clock, delaying the connect signal for a number of cycles and applying the connect signal to the control of the second clock only when a negative edge of the second clock is detected causing the second clock to disconnect from the output only at a negative edge.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: January 22, 2002
    Assignee: LSI Logic Corporation
    Inventors: Mark D. Rutherford, Arthur G. Rogers
  • Patent number: 6341056
    Abstract: A capacitor has a pair of plates separated by a capacitor dielectric material which is formed of multiple separate layers of different dielectric materials having different electrical characteristics. The different electrical characteristics are represented by linearity curves that curve relatively oppositely with respect to one another. Combining the different dielectric materials and separate layers achieves selected electrical characteristics from the overall capacitor dielectric material. The capacitor dielectric material may be formed with a top layer, a middle layer and a bottom layer. The middle layer may be formed of relatively high leakage dielectric and/or relatively high dielectric constant material, and the top and bottom layers may be formed of barrier material which is substantially resistant to leakage current and which exhibits a relatively lower dielectric constant.
    Type: Grant
    Filed: May 17, 2000
    Date of Patent: January 22, 2002
    Assignee: LSI Logic Corporation
    Inventors: Derryl D. J. Allman, Brian Bystedt
  • Patent number: 6340434
    Abstract: A method for chemical-mechanical polishing of a layer that is deposited on a surface of an integrated circuit substrate is described. The method includes: (1) immobilizing the integrated circuit substrate using a substrate holder such that the integrated circuit substrate surface is positioned against a surface of a polishing pad, which is mounted on a supporting surface; (2) a first stage of polishing the substrate surface including maintaining a predetermined difference between the rotational velocity of the polishing pad and the rotational velocity of the substrate holder allowing an endpoint of the chemical-mechanical polishing process of the layer to be detected; and (3) a second stage of polishing the substrate such that the rotational velocity of the polishing pad and the rotational velocity of the substrate holder are substantially the same to produce a substantially planar substrate surface.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: January 22, 2002
    Assignee: LSI Logic Corporation
    Inventors: Hiroshi Mizuno, Osamu Kinoshita, Tetsuaki Murohashi, Akihisa Ueno, Yoshifumi Sakuma, Kostas Amberiadis
  • Patent number: 6341375
    Abstract: An apparatus comprising a drive server, a control server and one or more decoder devices. The drive server may be configured to present one or more compressed data streams in response to one or more first control signals. The control server may be configured to present one or more of the compressed data streams in response to (i) one or more request signals and (ii) the one or more compressed data streams. The decoder devices may be configured to present a decoded video signal and a decoded audio signal in response to (i) one or more second control signals and (ii) the one or more compressed data streams. The navigation software, which traditionally is processed local to the decoder, may be processed on the control server. The control server may be enabled to control the remote decoder.
    Type: Grant
    Filed: July 14, 1999
    Date of Patent: January 22, 2002
    Assignee: LSI Logic Corporation
    Inventor: Daniel Watkins
  • Patent number: 6341367
    Abstract: A state machine is disclosed that is capable of providing improved performance as realized in a hardware embodiment while providing the flexibility of a software implemented state machine. The state machine is first implemented in software, and then is realized in a hardware embodiment based upon the software implemented state machine. Flexibility is added to the hardware realized state machine by providing registers for the hardware embodiment so that the register corresponds to states of the software implementation. As a result, at least one aspect of the hardware realized state machine may be modified without requiring redesigning the configuration of the hardware embodiment.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: January 22, 2002
    Assignee: LSI Logic Corporation
    Inventor: Kevin A. Downing
  • Patent number: 6341324
    Abstract: A microprocessor system includes a core CPU for instruction execution and a coprocessor interconnected with said core CPU for system control and exception processing. The coprocessor includes a plurality of exception handling registers including an exception program counter having a restart location stored therein for use after an exception is serviced, a status register having operating mode identification and interrupt enabling bits, and a configuration and cache control register. Interrupt processing is compatible with a plurality of instruction sets with a particular instruction set being designated by setting at least one bit in the configuration and cache control register. Registers are provided to save the operating state of the CPU prior to interrupt enable, the operating state of the CPU being restored after exception processing is completed and user mode is reestablished.
    Type: Grant
    Filed: October 6, 1995
    Date of Patent: January 22, 2002
    Assignee: LSI Logic Corporation
    Inventors: Robert L. Caulk, Jr., Hidetaka Magoshi, Kevin L. Daberkow
  • Patent number: 6340905
    Abstract: A clock tree deskew circuit dynamically minimizes skew in clock signals that synchronize operation of synchronized circuit components of an integrated circuit. The clock tree deskew circuit reduces the clock tree skew in repeated intervals over a period of time. The clock tree deskew circuit is then turned off to prevent unnecessary further adjustments to the clock signals, but can be turned back on when conditions change that alter the clock tree skew. The clock signals are paired together in a continuous loop, such that each clock signal is the first clock signal of the pair when paired with the next clock signal and is the second clock signal when paired with the one before it. The clock tree deskew circuit detects the absolute skew between each pair of the clock signals. The clock tree deskew circuit adjusts the first clock signal of each pair toward the second clock signal of the pair to reduce the skew between the two clock signals.
    Type: Grant
    Filed: June 19, 2000
    Date of Patent: January 22, 2002
    Assignee: LSI Logic Corporation
    Inventor: Richard T. Schultz