Abstract: A self-timing circuit with bit cell leakage current compensation provides a worst-case delay for a sense application read of a memory core. The self-timing memory circuit includes a worst-case dummy bit cell, a column of leakage current simulating dummy bit cells, and a dummy sense amplifier. The worst-case dummy bit cell is occupied to a dummy word line and a dummy bit line and is configured to drive the dummy bit line or dummy bit line pair to a first differential state when the dummy word line is asserted. The column of leakage current simulating dummy bit cells are coupled to the dummy tit line and are configured to delay the driving of the dummy bit line to the first differential state due to leakage current between the leakage current simulating dummy bit cells and the dummy bit line or bit line pair.

Abstract: A method designates nets of a circuit for detailed parasitic impedance extraction (e.g., calculation of parasitic resistance and/or capacitance components of circuit interconnects) by comparing an estimated net impedance parameter with other circuit characteristics, such as the output resistance of a driver cell or the gate capacitance provided by load elements connected to the net. One or more threshold percentage parameters may be used in the comparison. Also, based on the designation, the estimated net impedance parameter or the detailed parasitic impedance value may be used for calculating logic delay through a logic cell driving the net. A program stored on a computer readable medium also operates to evaluate the parasitic impedance of circuit interconnects relative to other circuit characteristics and, depending on this evaluation, calculates the logic delay of a logic cell driving the net using an estimated net impedance parameter or detailed parasitic impedance parameter.

Abstract: An integrated circuit oscillator input cell has an oscillator input pad, an oscillator feedback pad, a core terminal, an inverter and an electrostatic discharge protection circuit. The inverter has an inverter input, which is coupled to the oscillator input pad, and an inverter output, which is coupled to the oscillator feedback pad and the core terminal. The electrostatic discharge protection circuit includes a plurality of N-channel protection transistors, which are coupled to the oscillator input pad. The N-channel protection transistors are the only protection transistors that are coupled to the oscillator input pad.

Abstract: Two implementations of the inverse wavelet transform for use in an image decompression system do not waste computation power on the zero-valued values inserted into the data stream during an upsampling process. The implementation optimized for low-bandwidth applications toggles between even and odd modes each clock cycle. In even/odd mode, the transformed values are multiplied by the even/odd filter coefficients. The implementation optimized for high-bandwidth applications multiplies the transformed values by the even and odd filter coefficients seperately in two sets of multipliers and outputs two different results each clock cycle.

Abstract: Routing layers are assigned to connection segments in integrated circuit design. A routing description that includes connection segments and a vertex where at least two of the connection segments connect to each other is obtained. A penalty is determined for the vertex based on a potential layer assignment combination for the connection segments that connect at the vertex, and routing layers are assigned to the connection segments based on the determined penalty.

Abstract: A dynamic random access memory (DRAM) segment incorporates at least one shielding conductor spaced from a matrix of memory cells above the substrate and a well formed in the substrate which contains the memory cells. The shielding conductor primarily shields the memory cells from external noise signals created by other conductors. The isolating well primarily shields the memory cells from noise signals created by substrate currents and alpha particles. Among other features the DRAM employs a logically complementary pair of charge storage capacitors and differential sensing to avoid the influence of noise on a single memory capacitor. The shielding conductor is formed by a mesh of conductors or an integral conductor which overlays the matrix of cells and connects to the well. External power supplies and references are also connected to the well and the shielding conductors.

Abstract: A software test case client/server system provides selective access to a central repository of test case data used in testing a software program. A test case server stores and manages test case data in a central repository. A test client communicates between a test program and the test server to identify tests case data, and versions of such data, with desired read/write status required in testing a software program. A test program automates selection of test case data, software program test execution, and verification of software program results. In an exemplary embodiment, symbolic links and copies of test case data are recorded in a destination directory structure accessible by a software program under test. In an alternate embodiment, a revision control system (RCS) is used to access the central repository and provide copies of selected test case data in a destination directory structure accessible by a software program under test.

Abstract: A DRAM cell capacitor and access transistor are described. Capacitor formation, access transistor fabrication and cell isolation methods are integrated by using isolation trench sidewalls to form DRAM capacitors and access transistors. A doped silicon substrate adjacent to the vertical sidewalls of the isolation trench provides one DRAM cell capacitor plate. The DRAM capacitor also contains a dielectric material that partially covers the interior vertical sidewalls of the isolation trench. A conductive layer covering the dielectric material on the vertical sidewalls of the isolation trench forms the second capacitor plate and completes the DRAM capacitor. A vertically oriented access transistor is formed over top of the capacitor. To accomplish this, an isolation dielectric is deposited and patterned to provide a support structure for gate electrodes of the vertical access transistor above the trench sidewall capacitors.

Abstract: A method and system for decoding compressed MPEG2 bitstream video data utilizing a two row macroblock cache memory and algorithm for determining data overlap between a stored reference macroblock and a stored current macroblock to improve memory bandwidth requirements while producing specific decoding results required for MPEG2 video information.

Abstract: Techniques for fabricating metal-insulator-metal (MIM) capacitive structures by chemical vapor deposition (CVD) help avoid the formation of a porous metal oxide film at the interface between the lower electrode and the insulating layer. One method of fabricating an integrated circuit includes depositing a first titanium nitride electrode layer on a wafer by CVD and subsequently depositing an insulating layer on the first electrode. The insulating layer can comprise a material selected from the group consisting of titanium oxide (TiOx), titanium oxynitride (TiOxNy), titanium oxycarbonitride (TiOxNyCz) and silicon oxide (SiOx), and is deposited by CVD without exposing the first titanium nitride electrode to atmosphere. A second titanium nitride electrode layer also is deposited on the insulating layer by CVD. The various layers of the capacitive structure, including the insulating layer, can be deposited in situ in a single CVD chamber.

Abstract: An integrated circuit comprised of a customized circuit portion and a programmable logic portion that is interfaced to the customized circuit. The custom circuit and the programmable circuit are fabricated on a common semiconductor substrate to achieve maximum cost savings and performance advantages over implementations in which an external PLD or other programmable device is interfaced to a custom circuit. Suitably, the customized circuit is designed with an ASIC design flow to optimize the performance, power consumption, and size of the customized circuit. In the presently preferred embodiment, the programmable circuit comprises a plurality of programmable logic cells suitably generated by, in one embodiment, a PLD compiler. Ideally, the relative size and placement of said PLD with respect to said customized circuit are selectable during a design phase of said integrated circuit. This provides flexibility in determining how much of an interim device need be devoted to programmable circuitry.

Abstract: A method for detection of hot-swap of disk drives in a storage subsystem devoid of special circuits for such detection and for buffering of bus signals. Typical prior designs utilize special circuits such as disk drive canisters for physically and electronically connecting the disk drives to the storage subsystem. These canisters provided electronic buffering to reduce or eliminate transient (noise and glitch) signals associated with hot-swap drive removal and insertion. In addition, such canisters provided special purpose circuits to inform storage subsystem control modules that a possible insertion or removal occurred by forcing a reset of the interconnection bus in response to detection of such transient signals. The present invention provides for such detection without need for such complex (e.g., costly) special purpose circuits.

Abstract: An improved wafer scale integrated circuit is described which includes non-contact power and data transmission coupling. Wireless power and data coupling reduces the mechanical stresses and strains on the wafer, and makes better use of the wafer area. An additional benefit comes from allowing better heat transfer management. In one embodiment, power is provided by inductive coupling. Data flow into and out of the wafer is accomplished optically, using optical detectors to receive and light emitting diodes to transmit. Multiple devices are integrated onto the semiconductor wafer. Systems may be incorporated using the traditional die sites. Connections between systems are made in the space between die sites.

Abstract: An apparatus for etching a first side of a semiconductor wafer down to a desired level. The apparatus includes an etching chamber. The apparatus also includes a wafer chuck configured to engage the wafer by a second side of the wafer, and position the wafer in the etching chamber. The apparatus also includes a light source unit positioned such that light signals generated by the light source unit are directed into the wafer. Moreover, the apparatus includes a light receiving unit positioned such that the light signals generated by the light source unit emanate out of the wafer and are received with the light receiving unit. The light receiving unit includes a first optical material and a second optical material having an interface therebetween. The first optical material has a linear index of refraction, whereas the second optical material has a nonlinear index of refraction which is dependent on an intensity level of the light signals received with the light receiving unit.

Abstract: Apparatus, and an associated method, for performing error-correction operations to correct errors in a block of block-encoded data. Two ALUs are operable in parallel to perform finite-field mathematical operations and to calculate addresses used pursuant to the error-correction calculations. Instructions pursuant to which the ALUs are operable are stored in a memory device. The instructions are retrieved during operation of error-correcting calculations. The manner by which the error-correcting apparatus operates is alterable by appropriate alteration of the instructions stored at the memory device.

Abstract: Routing of electrical connections between cells arranged in cell columns on an integrated circuit (IC) die. Electrical connections are routed on a routing layer between cells located in a first cell column. An identification is made of an available off-grid resource capable of being used for wire routing that is both within the first cell column and on the routing layer. An electrical connection is routed between a first cell and a second cell located in different cell columns using at least a portion of the identified available off-grid resource. Also, an integrated circuit die which includes vertical power rails and vertical ground rails. Cell columns, including a first cell column and a second cell column, are each bordered by a vertical power rail and a vertical ground rail. A channel is provided between the first cell column and the second cell column.

Abstract: A method of making a metal interconnect stack for an integrated circuit structure is described comprising a main metal interconnect layer, an underlying TiN barrier layer and a titanium metal seed layer below the TiN barrier layer, and a barrier layer below the titanium metal seed layer to provide protection against chemical interaction between the titanium metal seed layer and an underlying plug in a via. The structure is formed by providing an integrated circuit structure having an insulation layer formed thereon with one or more metal-filled vias or contact openings generally vertically formed therethrough to have an upper surface thereon; forming a lower barrier layer such as a TiN barrier layer over the insulation layer and the upper surface of the metal in the one or more metal-filled vias; and subsequently forming the titanium seed layer over the lower TiN barrier layer.

Abstract: The present invention is a method and apparatus for systematically applying proximity corrections to a mask pattern, wherein the pattern is divided into a grid of equally sized grid rectangles, an inner rectangle comprising a plurality of grid rectangles is formed, an outer rectangle comprising a second plurality of grid rectangles and the inner rectangle is formed and proximity correction is applied to the pattern contained within the inner rectangle as a function of the pattern contained within the outer rectangle.

Abstract: Net routing is optimized in an integrated circuit device by dividing an integrated circuit design with a first group of substantially parallel lines in a first direction and with a group of substantially parallel lines in a second direction, with the second direction being substantially perpendicular to the first direction. A first routing graph is formed with vertices corresponding to locations where lines in the first direction and lines in the second direction cross, and nets are globally routed as a function of the first routing graph. The integrated circuit design is further subdivided with a second group of substantially parallel lines in the first direction, and a second routing graph is formed with vertices corresponding to locations where lines in the first and second groups of substantially parallel lines in the first direction cross lines in the group of substantially parallel lines in the second direction.

Abstract: The present invention is a method and apparatus for applying one-dimensional proximity correction to a piece of a mask pattern, by segmenting a first piece of a mask pattern with horizontal dividing lines into a plurality of segments, segmenting a second piece of said mask pattern with said horizontal dividing lines into a second plurality of segments, and applying proximity correction to a first segment from said first plurality of segments taking into consideration a second segment from said second plurality of segments.