Abstract: A method is provided for forming thin polysilicon transistor gates using dual doped polysilicon without reducing the ion implant energy. The method comprises depositing polysilicon over a region of a substrate, masking and implanting the polysilicon with dopant impurities to form the channel regions of one conductivity type, and removing the photo resist mask. The polysilicon layer is then masked to define the channel regions of the opposite conductivity type and is implanted with dopant impurities of the opposite conductivity type. Following the dual ion implantation, the photo resist mask is removed and the substrate may be annealed to activate the dopants in the polysilicon. The dual doped polysilicon layer is then polished using a chemical-mechanical polish to achieve a desired thickness for the polysilicon transistor gates. The polysilicon is subsequently masked and etched to define the polysilicon transistor gates.

Abstract: A method and system for displaying a series of video frames so that picture corruption from video channel underflows is avoided. The method comprises the steps of receiving a data stream with compressed video data for the series of video frames, storing the compressed video data in a channel buffer, processing a video frame if sufficient compressed video data for the video frame is stored in the channel buffer, and displaying a preceding video frame if insufficient compressed video data for the video frame is stored in the channel buffer. The system, which displays a series of video frames, also addresses the issue of video channel underflow. The video frames are received as compressed video data in a data stream that also includes size parameters, such as the vbv.sub.-- delay parameter in the frame headers of MPEG frames, for each video frame in the series of video frames.

Abstract: A method and system for compensating for code invariancies in a digital communication receiver is performed on demodulated signal data. A pre-Viterbi invariancy compensation is performed on the demodulated signal data to reverse a selected one of a number of possible transformations to create compensated signal data. The compensated signal data is then depunctured. The depunctured data is then decoded. An encoder encodes the decoded data. The encoded data and the depunctured data are then compared to determine equivalence. The pre-Viterbi invariancy compensation is performed to reverse a different one of the number of possible transformations to create the compensated signal data when the encoded data and the depunctured data are determined not to be equivalent. A post-Viterbi invariancy compensation is then performed on the decoded data to produce a set of compensated outputs. Thus, the post-Viterbi invariancy compensation reverses each one of the number of possible transformations on the decoded data.

Abstract: A large number of possible cell placements for an integrated circuit chip are evaluated to determine which has the highest fitness in accordance with a predetermined criteria such as interconnect congestion. Each cell placement, which constitutes an individual permutation of cells from a population of possible permutations, is represented as an initial cell placement in combination with a list of individual cell transpositions or swaps by which the cell placement can be derived from the initial cell placement. A cell placement can be genetically mutated and/or inverted by adding swaps to the list for its cell placement which designates cells to be transposed. Genetic crossover can be performed by transposing swaps between the lists for two cell placements. This cell representation and transposition method enables any type of cell transposition to be performed without loss or duplication of cells or generation of illegal placements.

Abstract: Data signal pins for a peripheral device are adaptively precharged during hot plugging to a voltage level depending on both the mode of operation (low voltage differential, high voltage differential, or single ended) and the actual signal voltages being employed for a particular mode. An active terminator bus provides an operating mode sensing signal, from which the operating mode of the bus and the actual signal voltage levels being employed may be determined. Signal pins on an edge connector for the device are connected, in sequence, to the corresponding ground, power supply, operating mode sensing signal, and data signal conductors of the bus.

Abstract: Provided is a method and composition for protecting alignment mark trench walls from attack by CMP slurry accumulating in an alignment mark trench during CMP processing. In a preferred embodiment, a metal organic chemical vapor deposition titanium nitride (MOCVDTiN) layer is deposited over a conventionally applied bulk tungsten layer prior to commencing CMP operations. This MOCVDTiN layer is resistant to CMP slurry attack. As a result, the tungsten trench profile remains a consistent and reliable alignment mark.

Abstract: A system for globally prioritizing and scheduling I/O requests from a plurality of storage users or clients to one or more storage objects. The system comprises a storage controller configured to receive I/O requests from the client workstations and prioritize and schedule those I/O requests in accordance with a scheduling algorithm. Specifically, the storage controller receives I/O requests from the storage users and places the I/O requests in memory queues associated with the particular storage users. The storage controller then selects the I/O requests from the various memory queues based on the scheduling algorithm.

Abstract: A phase-locked loop includes a phase detector, a charge pump, a resistor-less loop filter and a voltage-controlled oscillator ("VCO"). The phase detector has a reference input, a feedback input, and a charge control output. The charge pump is coupled to the charge control output, and the resistor-less loop filter is coupled to the charge pump. The VCO has a control voltage input coupled to the resistor-less loop filter, a clock output coupled to the feedback input and a plurality of delay elements which are coupled together in series to form a ring oscillator. Each delay element includes a delay element output. A MOSFET gate oxide capacitance is coupled between each delay element output and the charge control output.

Abstract: The present invention provides apparatus and a process for efficiently removing particles generated during a laser marking of the semiconductor wafer substrate, thereby improving the yield. The process of the invention for marking a semiconductor wafer substrate by a beam of laser radiation comprises the steps of flowing a gas over a marking region at a predetermined flow rate and removing the gas from the marking region at the same predetermined flow rate, thereby generating a gas flow having a predetermined flow rate over and adjacent the marking region so that particles produced from the semiconductor wafer substrate while it is being marked will be removed. In a preferred embodiment, the semiconductor wafer substrate may be mounted with its upper surface to be marked directed downwardly while the laser marking beam is directed upwardly to the substrate.

Abstract: An isolation trench in a silicon semiconductor substrate is provided with a barrier region containing nitrogen atoms formed in the trench, contiguous with the silicon semiconductor substrate surfaces of the trench. The novel isolation trench structure of the invention is formed by forming an isolation trench in a silicon semiconductor substrate; forming in the isolation trench a barrier region by treating the trench structure with nitrogen atoms from a nitrogen plasma; and then forming a silicon oxide layer over the barrier region in the trench to confine the nitrogen atoms in the barrier region. In a preferred embodiment, a silicon oxide liner is first formed over the silicon semiconductor substrate surfaces of the trench, and then the trench structure is treated with nitrogen atoms from a nitrogen plasma to form, on the silicon semiconductor substrate surfaces of the trench, a barrier layer which contains silicon atoms, oxygen atoms, and nitrogen atoms.

Abstract: A transmission system for transmitting a signal from a host to a transmission medium is disclosed. The transmission system includes a current-mode digital-analog converter, an on-chip low-pass filter, a line driver, and output impedance control. Further, a method for transmitting a signal from a host to a transmission medium using on-chip filtering is disclosed. The transmission system and method can be used in transmission of Ethernet signals onto an unshielded twisted pair cable. In addition, with appropriate modification, the transmission system and method can be used for transmitting ATM or other signals onto a transmission medium.

Abstract: A device to turn on a disk formatter's write gate and NRZ line drivers with minimal delay from a sector pulse. The device utilizes a look-ahead scheme to asynchronously qualify a sector pulse to drive the write gate and enable the NRZ output drivers. The write gate and NRZ line drivers are conditionally enabled by a sector pulse and are held in the enabled state until the disk formatter provides an enable signal. The enabled NRZ line drivers provide binary zeros until actual data is provided to the drivers.

Abstract: Disclosed is a failure analysis tool including a production tester electrically coupled to a test IC in such a manner that it can test the IC in a conventional manner (e.g. by providing a series of dynamic vectors), and also provide an OBIC signal to an OBIC detection system. This is accomplished by providing power to the IC through a voltage source having a non-zero internal resistance while the OBIC signal is generated, thus preventing the OBIC signal from shorting to ground when it is received at the power supply. Failure analysis is conducted by first performing functional testing with a production tester until a failing state is identified. While this functional testing is being performed, the internal resistance of the voltage source is set to zero. Then, when the failing state is identified, the internal resistance of the voltage source is set to a non-zero value and the IC is scanned by an optical beam to generate OBIC signals indicating the locus of the failure.

Abstract: An object of the present invention is to provide for a method and apparatus to partition high fanout nets into smaller subnets. Said method includes the steps of identifying elementary pairs of pins in the net, each such elementary pair defining a line; eliminating lines such that a planar graph is formed; eliminating further lines such that a spanning tree is formed, said spanning tree connecting each pin in the net; identifying basic elements, each basic element forming a portion of said spanning tree; and constructing a connected cover for said net, said connected cover comprising a plurality of said basic elements.

Abstract: A routing scheme for a multilayer printed wiring board or semiconductor package is disclosed. Each of a first group of electrical contacts such as bond pads is disposed on a first surface and is electrically coupled to one of a plurality of conductive surface connectors such as vias. Each of a second group of electrical contacts is disposed on the first surface and is routed by one of a second plurality of traces. Each of a plurality of short traces couple each of the bond pads in the first group with corresponding ones of the vias, which in turn are electrically coupled to one of a plurality of first traces on the second surface. The orientation between certain electrical contacts in the first group and their associated vias is different than the orientation between certain other electrical contacts in the first group and their associated vias. This varying orientation allows greater routing density on the second surface.

Abstract: A DMA controller including an XOR FIFO buffer and XOR circuitry for computation of parity. The DMA controller resides within a RAID controller and establishes a direct data connection from host memory to subsystem local memory in order allow the CPU to perform other functions. The DMA controller accesses data segments from host memory corresponding to blocks of data within a disk stripe. As the data is transferred from host memory to subsystem local memory, the XOR circuitry simultaneously computes the parity corresponding to the successive data segments. Computing parity substantially simultaneously with the DMA data transfer reduces memory bandwidth utilization on the memory bus of the RAID controller. The parity is stored in the XOR buffer. Once parity is computed for a portion of data segments corresponding to a data stripe, the parity is transferred to local memory for retention.

Abstract: Radio frequency photo conductive decay is used to monitor a small piece of high-grade silicon to determine if copper contamination has been removed from a probe tool. A probe tool is placed in contact with a small "waferette" of silicon repeatedly until the copper signal is diminished, indicating that the tool may be used for other products without concern for copper contamination.

Abstract: In a storage target device controller capable of managing multiple command contexts, methods and associated apparatus are provided for enabling simultaneous, independent operation of the disk channel and the host channel. In a multi-context target device controller, an active context initiates a requested exchange of data blocks between the host channel and the disk channel of the target device. The controller may swap the active context with an inactive context to better utilize resources of the target device such as the host channel bandwidth. The present invention provides for continued independent operation of the host channel and the disk channel. Counters associated with the active context are only updated by operation of the disk channel if the active context is the initiating context of the disk operations.

Abstract: Method and apparatus for accelerating write operations logging write requests in a log structured cache and by expanding the log structured cache using a cache-extension disk region. The log structured cache include a cache memory region partitioned into one or more write cache segments and one or more redundancy-data (parity) cache segments. The cache-extension disk region is a portion of a disk array separate from a main disk region. The cache-extension disk region is also partitioned into segments and is used to extend the size of the log structured cache. The main disk region is instead managed in accordance with storage management techniques (e.g., RAID storage management). The write cache segment is partitioned into multiple write cache segments so that when one is full another can be used to handle new write requests. When one of these multiple write cache segments is filled, it is moved to the cache-extension disk region thereby freeing the write cache segment for reuse.

Abstract: A composite metal line structure for an integrated circuit structure on a semiconductor substrate is disclosed which comprises: a low resistance metal core layer; a first thin protective layer of electrically conductive material on the upper surface of the metal core layer capable of protecting the metal core layer from reaction with tungsten; a layer of tungsten formed over the first protective layer to function as an etch stop layer for vias subsequently formed in an overlying dielectric layer; and a second thin protective layer of electrically conductive material over the tungsten layer and capable of functioning as an antireflective coating (ARC).