Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first control signal and a second control signal in response to (i) a digital input signal and (ii) a clock signal. The second circuit may be configured to generate a third control signal by scrambling the first control signal. The third circuit may be configured to generate a pulse width modulated output signal in response to (i) the second control signal and (ii) the third control signal.

Abstract: A method and apparatus for mirroring currents in application specific integrated circuits provides higher current mirroring accuracy than previously obtainable with matched active devices by using small groups of resistors with local matching to create a summing node which represents the average voltage across the source resistors of the active output devices and by forming a reference resistor through the combination of resistors from the local resistor groups such that the reference resistor has properties which will largely cause cancellation of location gradients and initial value variation in the resistor groups. An error amplifier compares the voltage at the summing junction with the voltage across the reference resistor and adjusts its output voltage to drive the paralleled gates of each active mirror output device such that the summing junction and reference resistor voltages remain equal.

Abstract: An apparatus and method for aligning any number of multiple parallel channels of data signals according to a single clock is provided. The synchronization process is accomplished through the use of a First-In-First-Out (FIFO) principle and individual storage elements implementing the FIFO principle for each received data channel. Each channel's data signals are read into a corresponding storage element, maintained in order, and read out upon the assertion of read signals in synchronization with a designated single clock signal. The apparatus and method preferably uses indications of data ready to be read from a storage element implementing the FIFO principle and the presence of a master clock signal to activate the reading of the data from the corresponding storage element. Therefore, each data channel is fully aligned with the master clock signal. The clock-data alignment function may be implemented for a 100BASE-T4 receiver.

Abstract: A method of synthesizing integrated circuit chip (IC) designs having clock signals defined internal to a module comprising the steps of mapping the IC design to a target technology with the internal clock defined, removing definitions of the internal clock, re-synthesizing the IC design, and re-defining the internal clock using new names of clock sources.

Abstract: An aerial image produced by a mask having transmissive portions is simulated by dividing the transmissive portions of the mask into primitive elements and obtaining a spatial frequency function corresponding to each of the primitive elements. The spatial frequency functions corresponding to the primitive elements are combined to obtain a transformed mask transmission function, and the transformed mask transmission function is utilized to generate a simulation of the aerial image.

Abstract: The present invention retrieves data across independent computer nodes of a server cluster by providing for I/O shipping of block level requests to peer intelligent host-bus adapters (hereinafter referred to as HBA). This peer-to-peer distribution of block I/O requests is transparent to the host. The HBA has the intelligence to decide whether to satisfy a block I/O request locally or remotely. Each HBA driver utilizes the I2O protocol, which allows peer-to-peer communication independent of the operating system or hardware of the underlying network. In a first embodiment of the present invention, local and remote storage channels, within a node, are supported by a single HBA. In a second embodiment of the present invention, local storage channels, within a node, are supported by one HBA, and the remote storage channel, within a node, is supported by a separate HBA.

Abstract: One or two, or more, additional conductive layers, separated from one another (if two or more) and separated from a patterned (signal) conductive layer are formed in a flexible substrate, for mounting a semiconductor die in a semiconductor device assembly. These additional layers are used as separate planes for carrying power and/or ground from outside the assembly to the die, on a separate plane from signals entering or exiting the die. TAB processes are disclosed for cutting, bending and bonding inner and outer portions of selected signal layer traces to respective inner and outer edge portions of the additional conductive layer(s), including a two-stage process of (1) first cutting, bending and tacking the selected traces to the additional layer(s), and then (2) repositioning a bonding tool and securely bonding the selected traces to the additional layer(s). A tool (die pedestal) for aiding in the assembly process is also disclosed.

Abstract: A polishing pad for chemical-mechanical polishing of an integrated circuit surface is described. The polishing pad includes a first polishing area having a first value of a physical property; and a second polishing area having a second value of said physical property, which said second value is different from the first value, such that during chemical-mechanical polishing of an integrated circuit surface, the integrated circuit rotates and oscillates on the polishing pad so that a substantial portion of the integrated circuit surface contacts both the first and second polishing areas, wherein a width of said first and second polishing areas is greater than about 40 mils.

Abstract: A system and method for a differential charge pump with reduced charge-coupling effects for use in integrated circuits such as a phase-lock loop are disclosed. The charge pump includes a first branch, a second branch, and a charge device. The first branch includes a first current source and sink coupled to a power supply and ground, respectively, a first current steering device coupled between the first current source and sink, and a first buffer coupled to the first current steering device between a first charge node and a first damp node. The second branch includes a second current source and sink coupled to a power supply and ground, respectively, a second current steering device coupled between the second current source and sink, and a second buffer coupled to the second current steering device between a second charge node and a second damp node.

Abstract: The present invention includes a method of transferring data when some of the data is masked. A mask table is provided to a storage device where it is duplicated and stored with the duplicate. The duplicate data is compared to the original data for a data protection function. A mask index counter and mask bit counter maintain provide values for specific data that are to be processed. The counters are programmable so that if a transfer error occurs, counter values for the next data after the previously transferred good data is calculated and loaded therein. The present invention also has the capability not to transfer the last requested sector if that sector is masked. The present invention evaluates whether a stop count value equals a stop threshold value when a sector is identified as being masked. The stop count value is incremented for each sector that is read from the first storage device, regardless of whether that sector is to be transferred or masked.

Abstract: A method and system for preventing information losses during alternative frequency searches by a receiving unit in a communication system in which data is channel coded, interleaved, and segmented into a plurality of frames. The method comprises the steps of discontinuing demodulation at a predetermined time before a frame ends, inserting zero values into the frame, and performing a search for alternative frequencies while continuing to insert zero values into the frame and then a next frame. After the search is completed, insertion of zero values is discontinued and demodulation is resumed. In one preferred version, the receiving unit comprises a mobile radio station operating at a serving frequency. The step of inserting zero values is followed by a step of programming the mobile radio station to a search frequency and waiting for the mobile radio station to settle.

Abstract: The present invention provides a method and apparatus for conditioning a polishing pad in which slurry is directed under pressure at the polishing pad. Additionally, energy (i.e., ultrasonic energy) may be added to the slurry as it is directed towards the polishing pad, wherein embedded material in the polishing pad is removed or dislodged.

Abstract: Provided is a die clip for use in semiconductor flip chip packaging as a replacement for the conventional combination of a heat spreader and stiffener, a packaging method using the die clip, and a semiconductor package incorporating the die clip. In a preferred embodiment, the die clip is a piece of high modulus, high thermal conductivity material shaped to attach over a die on the surface of a packaging substrate. The die clip closely engages the die while leaving some space open around the perimeter to provide access to the die. An underfill material may then be dispensed into the gap between the die and the substrate through an opening in the die clip. The underfill material is then cured, the die clip providing a heat sink and keeping the die and substrate flat and immobile during and after the curing process. A BGA process may then be used to apply solder balls to the underside of the substrate for subsequent bonding of the package to a circuit board for use.

Abstract: An integrated circuit structure is provided with an inductor formed therein which comprises a metal coil on an insulated surface over a semiconductor substrate, and a high magnetic susceptibility cobalt/nickel metal core located adjacent said metal coil, but spaced therefrom by one or more insulation layers. In one embodiment, the high magnetic susceptibility cobalt/nickel metal core is placed between lower and upper portions of the metal coil which are interconnected together by filled vias. In another embodiment, the metal coil is formed in a serpentine shape in one plane on an insulated surface over the semiconductor substrate, and the high magnetic susceptibility cobalt/nickel metal core is formed over the serpentine coil, but spaced from the serpentine coil by another insulation layer.

Abstract: A transceiver pair is connected by a plurality of high speed serial lines that are tightly integrated into an enhanced communications system. The communications system includes a base transceiver, a remote transceiver, and a plurality of high speed serial lines operably coupled between them. The base transceiver includes a first base input port for receiving parallel data, a plurality of first base output ports for outputting serialized data and a plurality of base serializers operably coupled between the first base input port and the plurality of first base output ports. The plurality of base serializers convert the parallel data into the serialized data. A base input demultiplexer is operably coupled between the first base input port and the plurality of base serializers.

Abstract: A vibration dampening mechanism for operative arrangement with a data storage media drive canister, having: a cantilevered dampening spring secured to a surface of, or integral with, a side of a housing for the drive canister. The spring has a free end that can extend over an aperture through the housing side. The spring can comprise a bent portion, having an outer bend surface, between a secured end and the free encl. When installed in a canister support structure, this outer bend surface will contact an under surface of the structure causing the bent portion to at least partially flatten; the free end may deflect into the aperture. Also, a storage media drive vibration dampening system for operation with a media drive canister support structure having: a cantilevered dampening spring secured to, or integral with, a side of a drive canister housing.

Abstract: Digital interference rejection of a signal is accomplished by first converting the signal to digital. Then a second signal is generated and mixed with the first signal. This combined signal is then filtered. The signal can then be scaled as needed, resulting in a finely tuned, interference free signal.

Abstract: An integrated circuit including a substrate having a memory area and a non-memory area. An embedded memory is fabricated on the substrate within the memory area. First and second semiconductor cells are fabricated on the substrate within the non-memory area. An electromagnetic shield covers substantially memory area. A routing layer is fabricated over the memory and non-memory areas and over the electromagnetic shield. A signal wire is electrically coupled between the first and second semiconductor cells and has a conductive segment which is routed within the routing layer and extends over the memory area.

Abstract: A computer network is provided with a low-complexity sequence identification number determination method. In one embodiment, the computer network comprises a local node coupled to a remote node by a serial communications link to conduct data exchanges with the remote node. Each data exchange is provided with an exchange identification number, and each data exchange is made up of sequences of consecutive frames. Each sequence transmitted from the local node is assigned a sequence identification number by the local node. To maintain the uniqueness of the serial identification numbers of concurrently active sequences, a portion of each serial identification number is set equal to the exchange identification number of the data exchange of which the sequence is a part. The exchange identification number may be one assigned to the exchange by the remote node. In one implementation, the sequence identification number is a byte having the six most significant bits set equal to the exchange identification number.

Abstract: A method is provided for forming thin polysilicon transistor gates using dual doped polysilicon without reducing the ion implant energy. The method comprises depositing polysilicon over a region of a substrate, masking and implanting the polysilicon with dopant impurities to form the channel regions of one conductivity type, and removing the photo resist mask. The polysilicon layer is then masked to define the channel regions of the opposite conductivity type and is implanted with dopant impurities of the opposite conductivity type. Following the dual ion implantation, the photo resist mask is removed and the substrate may be annealed to activate the dopants in the polysilicon. The dual doped polysilicon layer is then polished using a chemical-mechanical polish to achieve a desired thickness for the polysilicon transistor gates. The polysilicon is subsequently masked and etched to define the polysilicon transistor gates.