Abstract: The present invention provides for a shielded capacitor in a digital CMOS fabrication process. The shield capacitor comprises a first surface (also known as a top plate) and a second surface (the bottom plate). The bottom plate has two portions which are connected, and the two portions of the bottom plate are positioned to sandwich the top plate in between the portions. A polysilicon layer is fabricated between the plates and the substrate of the semiconductor to isolate the plates from the substrate. To build the shielded capacitor, the polysilicon layer is fabricated first, then the plates are built on top of the polysilicon layer. The polysilicon layer is silicized and is often connected to the ground.

Abstract: An optical disk controller reads CD-ROM disks at high speeds that commonly produce errors. Errors in the headers that identify sectors are tolerated by the sector-search hardware. The disk-controller firmware writes a virtual target register the previous sector's header's minutes, seconds, frame (MSF), which is one less that the desired sector's MSF, or MSF-1. A physical target that precedes the virtual target is searched for. The physical target precedes the desired sector by N sectors, so that the physical target is MSF-N. When the physical target matches a header read from the disk, a good sector found flag is set. The physical target is then incremented for each new sector and compared to the virtual target. Once the physical target matches the virtual target, the following sector is buffered to the host. The raw header from the disk is stored and error corrections are made using the error correction byte following the sector's data.

Abstract: High voltage and low voltage devices are provided on a common semiconductor substrate. An integrated semiconductor circuit includes a semiconductor substrate of a first conductivity type. Well regions of a first conductivity type and well regions of a second conductivity type are formed in the substrate. Low voltage devices are formed in well regions of the first conductivity type. A high voltage device includes source/drain regions of the second conductivity type formed, respectively, in well regions of the second conductivity type, an oxide region disposed on a surface of the substrate located above a region of the substrate that serves as a channel for the high voltage device, and a gate region disposed on the oxide region.

Abstract: A demodulator for digital-versatile disk (DVD) optical disks converts 16-bit codewords stored on the disk into 8-bit symbols or user bytes that are sent to the host after error correction. Rather than use the modulation tables in the DVD specification in reverse, the entries in the modulation table are sorted and combined. The four states stored in the DVD modulation table are reduced to two states or conditions. All entries from states 1 and 4 are sorted into unique tables that have unique mappings of codewords to symbols. Since the unique mappings are not sequence or state dependent, no state information is stored in the unique tables. Entries from states 2 and 3 are sorted into duplicates tables that have duplicate mappings, where a codeword can map to two different symbols, depending on the state sequence. One of the two symbols is chosen based on bits in the following codeword, which is the next state.

Abstract: A programmable audio/video encoder capable of receiving an encoding algorithm from an external digital information source. In one embodiment, the system accepts recordable DVD disks having a read-only sector for storing customized video encoding algorithms and programs the programmable video encoder with the customized video encoding algorithms prior to encoding and recording a video signal on the disk. By designing the video encoding algorithms to optimize one or more of a number of desirable attributes, the DVD media vendors can then create “classes” of recordable DVD disks, i.e. high capacity, high quality, high speed, high image detail, high color resolution, variable frame rate, etc. One programmable video encoder for this embodiment would include an instruction memory for storing the customized video algorithms, a video buffer for buffering the video signal, and a CPU which encodes the video signal according to the customized video algorithms.

Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that wire routine be done correctly to avoid any congestion of wires. Congestion of wires can be determined by actually routing of the wires to connect the cells; however, the routing process is computationally expensive. For determination of congestion, the only required information are the location of the connections, or edges, to connect the pins of the IC. The present invention discloses a method to quickly provide a good estimate of the location of the edges, or connections for an IC. The present invention provides for a method to determine all the edges and superedges (bounding boxes, or areas where an edge will take space) of an IC without requiring to determine the actual routing of the wires of an IC.

Abstract: A method for assigning signals to specific metal layers through the use of interconnect wire load models that are metal layer dependent. The method allows synthesis and layout tools to route signal wires on select metal layers at an early stage in the design process. A technology library for use in designing integrated circuits is provided. In addition to traditional library components such as logic gate information, the technology library includes routing wire load models that are metal layer dependent. The wire load information reflects the electrical properties of signal wires formed on different metal layers, and provides more accurate timing estimates than generic wire delay values. The additional information influences the delay calculations of the synthesis process in such a way that the delay a signal encounters on a specific metal layer can be approximated very closely. Of significance to the present invention, a wire-metal layer attribute file is compiled by the synthesis process.

Abstract: A circuit and method is provided for initiating an exception routine using exception information stored within architectured registers. Exception information is generated in response to a memory access exception caused by a speculative load instruction for loading a first register data from memory. The exception information, once generated, is stored within a first register. Thereafter, an instruction for operating on data stored in a second register is received and decoded. In response, the second register is checked to determine whether the second register contained exception information. If the second register contains exception information, then an exception routine is initiated. If, however, a second register does not contain exception information, then the instruction is executed and data within the second register is used in the execution.

Abstract: A bridge translates addresses between a first bus and a second bus, with a larger address space capability. The bridge stores “high address” information and combines that information with address information from a device on the first bus when the device desires to transfer information from the first bus to the second bus. The bridge accesses high address information using information identifying the device.

Abstract: An optical disk system is presented which stores index information allowing playback of selected portions of a presentation recorded upon an optical disk, along with an associated method. The index information includes navigation data indicating the physical location of a beginning of a selected portion of a presentation stored upon the optical disk. One embodiment of the optical disk system includes a memory unit operably coupled to a disk drive unit and an input device. The disk drive unit retrieves identification data, encoded video data, and navigation data stored upon an optical disk (e.g., a DVD). The encoded video data may be, for example, a recorded presentation such as a movie. The input device produces an output signal in response to user input, wherein the output signal indicates a beginning of a selected portion of the encoded video data. The memory unit includes a non-volatile portion for storing the identification data and the index information.

Abstract: A control system in a data storage apparatus and associated methods for attempting to accommodate the vibrations resulting from rotating a data storage medium. The control system comprises a neural network which utilizes detected vibrations resulting from the rotation of data storage media to learn the characteristics of the rotational imbalance of rotating data storage media. Thereafter, the rotation of a data storage medium and/or movement of a data head is controlled based on the characteristics learned.

Abstract: According to the present invention, bitlines may be precharged to the supply voltage (Vdd) less a multiple of the transistor threshold voltage (Vtn), where the multiple is greater than or equal to 2. By precharging to a lower voltage, power consumption is reduced and memory speed is increased.

Abstract: In a 100BASE-T4 protocol network, the “carrier_status” signal associated with an incoming packet on a PMA of a given port of a Clause 27 repeater is obviated and a direct connection between PMAs and a Clause 27 repeater in the network is eliminated by transmitting synthetic preamble signals over the PMA-Repeater Data Interface to the Clause 27 repeater corresponding to the given port at an early time prior to the time that the actual preamble information of the packet is transmitted over that data interface. Receipt of the synthetic preamble signals causes the repeater to awaken and to repeat the synthetic preamble signals to other ports of the repeater. In turn, the other ports become quiet in anticipation of data to be repeated from the given port to the other ports of the repeater.

Abstract: Process monitoring circuitry according to the invention incorporates test structures placed across an integrated circuit die to monitor the performance of the fabrication process across the die. The integrity of the semiconductor fabrication process used to manufacture a particular integrated circuit is ascertained by comparing data extracted the test structures by automated test equipment (ATE) to simulation values. In one embodiment in the invention, the process monitoring circuitry comprises inverters arranged in a generally linear fashion. The inverters may be composed of simple CMOS inverters or other logic gates configured as inverters. The logic gates are arranged in horizontal and/or vertical test paths in which the gates are disposed across various sections of the integrated circuit die. An input test pad and an output test pad for each test path are provided at opposing sides of the integrated circuit die.

Abstract: A low power, high performance circuit for magnitude and group delay shaping in continuous-time read channel filters is disclosed. The circuit generally comprises a first and a second biquadratic circuit, each having an input, a band pass, and a output low pass node, where the second biquadratic input node is coupled to the first biquadratic output node, and a first and second transconductor coupled to the first biquadratic band pass node and also to the second biquadratic band pass and low pass output nodes, respectively. The first and second transconductors are preferably programmable transconductors.

Abstract: A method and apparatus for transferring data from a host to a node through a fabric connecting the host to the node. A chip architecture is provided in which a protocol engine provides for on ship processing in transferring data such that frequent interrupts from various components within the chip may be processed without intervention from the host processor. Additionally, context managers are provided to transmit and receive data. The protocol engine creates a list of transmit activities, which is traversed by the context managers, which in turn execute the listed activity in a fashion independent from the protocol engine. In receiving data, the context managers provide a mechanism to process frames of data originating from various sources without requiring intervention from the protocol engine. When receiving data, the context managers are able to process frames from different sources, which arrive out of order.

Abstract: A low impact buffer structure disposed in unused silicon area in a signal line routing channel between logic cell rows of an integrated circuit. In a buffer cell according to the invention, power to the buffer is provided by the power supply rails of one or more nearby logic cell rows. Both the connections to the supply rails and the connections between the transistors of the buffer cell are constructed of a polysilicon material and/or lower metal layer. In this manner, the buffer cell does not significantly impact the routing of metal signal lines in the signal line routing channel. In addition, the buffer cells can be arranged in a “staggered” configuration wherein separate buffers are provided in individual routing tracks of a signal line routing channel, further reducing the possibility of interference with normal signal routing.

Abstract: Lifetime of a short-channel NMOS device is increased by modifying distributions of electrically active LDD dopant at boundaries of the device's LDD regions. The LDD dopant distributions are modified by implanting counter-dopants at the boundaries of the LDD regions. Group III counter-dopants such as boron and group IV elements such as silicon alter activation properties of the LDD dopant. The dopant distributions are modified at the device's n-junctions to reduce the maximum electric field displacement at an interface defined by the device's gate and substrate. The dopant distributions can be further modified to shape the n-junctions such that hot carriers are injected away from the gate.

Abstract: Methods and apparatus for planarizing the surface of a semiconductor wafer by applying non-uniform pressure distributions across the back side of the wafer are disclosed. According to one aspect of the present invention, a chemical mechanical polishing apparatus for polishing a first surface of a semiconductor wafer includes a polishing pad which polishes the first surface of the semiconductor wafer. The apparatus also includes a first mechanism which is used to hold, or otherwise support, the wafer during polishing, and a second mechanism that is used to apply a non-uniform pressure distribution through the first mechanism, directly onto a second surface of the wafer. The second mechanism is further used to facilitate polishing the first surface of the semiconductor wafer such that the first surface of the semiconductor wafer is evenly polished.

Abstract: An integrated circuit oscillator input cell has an oscillator input pad, an oscillator feedback pad, a core terminal, an inverter and an electrostatic discharge protection circuit. The inverter has an inverter input, which is coupled to the oscillator input pad, and an inverter output, which is coupled to the oscillator feedback pad and the core terminal. The electrostatic discharge protection circuit includes a plurality of N-channel protection transistors, which are coupled to the oscillator input pad. The N-channel protection transistors are the only protection transistors that are coupled to the oscillator input pad.