Abstract: An information circuit in a semiconductor device suitable for encoding and retrieving a bit of information. The information circuit includes an input circuit and an output circuit. The input circuit includes an input node coupled to an input terminal of a transistor. The output circuit includes a load device, a fuse circuit, and first and second output terminals of the transistor all coupled in series between a power supply terminal and a ground terminal. The impedance of said fuse circuit is preferably alterable between an initial impedance and an altered impedance. An output node of said information circuit is coupled to said output circuit. The information circuit is configured such that the output node voltage is indicative of said impedance of said fuse circuit when said input node is biased to a “read” state, said power supply terminal is biased to a power supply voltage, and said ground terminal is grounded.

Abstract: An electrical interconnection structure on an integrated circuit is provided that has a) a substrate layer; b) a diffusion barrier on the substrate layer; c) a copper layer on the diffusion barrier; and d) a copper oxide layer on the copper layer. Methods of making such an interconnection structure is also provided. Such an interconnection structure may be used as a rectifier to prevent damage of sensitive devices from voltage spikes.

Abstract: A multiple-channel data communication buffer includes a transmit first-in-first-out (“FIFO”) circuit and a receive FIFO circuit. The transmit and receive FIFO circuits each include a write pointer array, a read pointer array and a single memory device having a data input, a data output, a write address input, a read address input and a plurality of logical channels from the data input to the data output. The write pointer array has a write pointer for each of the logical channels and applies a selected one of the write pointers to the write address input based on a write channel number input. The read pointer array has a read pointer for each of the logical channels and applies a selected one of the read pointers to the read address input based on a read channel number input.

Abstract: Tile-based routing between a bump pad and an input/output (I/O) device for implementation on a flip-chip integrated circuit (IC) die. A trace is routed between the bump pad and a position corresponding to a first I/O slot, the first I/O slot being at least partially occupied by the I/O device. A position is obtained for a device pad for the I/O device. The trace is then extended into an area corresponding to the position obtained for the device pad. It is a feature of this aspect of the invention that the trace extension extends the trace into a pad area for a second I/O slot, the second I/O slot being at least partially occupied by the I/O device. The invention also concerns a flip-chip integrated circuit (IC) die that includes a bump pad, an input/output (I/O) device, and a device pad electrically connected to the I/O device and disposed vertically adjacent to a portion of the I/O device.

Abstract: A system and method are disclosed for reading data from a magnetic disk. The method includes generating a preamplified data signal by reading the magnetic state of the disk using a magnetoresistive head. The preamplified data signal is capacitively coupled to a variable gain read channel amplifier. The variable gain read channel amplifier has an input, an output, and a programmable gain. The input of the variable gain read channel amplifier has a variable gain read channel amplifier input resistance. The occurrence of a thermal asperity event is detected and an adjustment is made to the variable gain read channel amplifier input resistance to compensate for the thermal asperity event. An adjustment to the programmable gain of the variable gain read channel amplifier is made to compensate for the adjustment to the variable gain read channel amplifier input resistance.

Abstract: A method of fabricating an integrated circuit using photolithography and an antireflective coating. An antireflective coating is formed on a substrate wherein the antireflective coating is electrically polarizable. A photoresist coating is formed on the antireflective coating on a side opposite from the substrate and the photoresist is exposed to activating radiation. The antireflective coating is subjected to an applied electric field at substantially the same time as the photoresist is exposed to activating radiation. The radiation absorption coefficient of said antireflective coating is increased and the refractive index of said antireflective coating is changed to be substantially equal to the refractive index of said photoresist coating.

Abstract: A sense amplifier includes a voltage supply terminal, first and second differential bit line inputs and a differential amplifier. The differential amplifier has first and second amplifier inputs, which are coupled to the first and second differential bit line inputs, respectively, and has an amplifier output. A first transistor is coupled between the voltage supply terminal and the first bit line input and has a current control terminal coupled to the second bit line input. A second transistor is coupled between the voltage supply terminal and the second bit line input and has a current control terminal coupled to the first bit line input.

Abstract: A semiconductor package is disclosed. According to one embodiment, the package comprises a substrate having a top surface with traces thereon and a bottom surface with solder balls thereon, the substrate comprising at least three material layers defining at least four substantially planar metal layers, wherein one of the metal layers comprises a reference layer that serves as a reference to both traces on a metal layer above the reference layer and traces on a metal layer below the reference layer. A semiconductor die is mounted to the substrate and bonding wires electrically connect the semiconductor die to the traces on the top surface of the substrate. The traces on the top surface of the substrate are electrically connect to the solder balls through vias and possibly through routing on another metal layer.

Abstract: One aspect of the invention relates to a flip-chip semiconductor package. In one version of the invention, the flip-chip semiconductor package includes a package substrate having an upper surface, a lower surface and a plurality of conductive traces, the upper surface having an upper plurality of electrical contacts coupled to the conductive traces, the lower surface having a lower plurality of electrical contacts coupled to the conductive traces, the lower plurality of electrical contacts being attachable to electrical contacts on a printed circuit board; a semiconductor die having an active surface and a non-active surface, the active surface having a plurality of circuit elements and a plurality of bond pads formed thereon, the bond pads being attached to the upper plurality of electrical contacts by solder bumps, the non-active surface having a plurality of grooves formed thereon; and a heat sink attached to the non-active surface of the semiconductor die.

Abstract: An interface for connecting a first vacuum source to a first vacuum apparatus, and for selectively connecting the first vacuum source and the first vacuum apparatus to a second vacuum apparatus without venting the first vacuum apparatus. A third fitting is connected to the first vacuum source, and makes a hermetic seal between the first vacuum source and the interface. A vacuum source line, having a first end and a second end, is connected by its first end to the third fitting. The vacuum source line receives a vacuum from the first vacuum source, and conducts the vacuum through the vacuum source line. A first tee section, having a first end and a second end, is connected by its first end to the second end of the vacuum source line. The first tee section receives the vacuum from the vacuum source line and conducts the vacuum through the first tee section.

Abstract: An on-chip misalignment indicator for measuring misalignment between layers of an integrated circuit die employs a first contact, and a second contact. A current path between the first and second contacts having a resistance that varies as a function of misalignment between successive layers of the integrated circuit die. Similarly, a method for detecting misalignment between layers of an integrated circuit die involves passing and measuring a current between a first contact. The amount of the current being indicative of an amount of misalignment between layers of the integrated circuit die.

Abstract: A method for refining the position of linearly aligned cells on the surface of a semiconductor chip is disclosed herein. The method comprises defining an array of spaces between cells based on maximum and minimum cell positions, establishing a minimum spacing between cells, and linearly shifting cells in a predetermined manner such that no cells are closer to one another than the minimum spacing between cells. Linear shifting is accomplished by shifting any cell in a positive direction if the spacing associated the cell is less than the minimum spacing between cells; shifting any cell in a negative direction if the spacing associated with the cell is greater than the minimum spacing between cells, but only if all cells on the negative side of the cell have been shifted in their maximum negative direction; and performing positive shifting and negative shifting until all cells have been shifted such that no space between cells is less than the negative space between cells.

Abstract: A system and method for reduced metastability errors in an analog-to-digital converter (“ADC”) are disclosed. The ADC comprises comparators configured to output a thermometer code and a thermometer-to-binary encoder for converting the thermometer code to a digital output.

Abstract: The method and apparatus provides a data processing system. The data processing system includes a primary bus, a secondary bus, and a host processor connected to the primary bus. The data processing system includes a first secondary processor connected to the primacy bus and the secondary bus. Additionally, a second secondary processor is connected to the secondary bus. The first secondary processor and the second secondary processor forms cascaded processors for input/output functions. Selected functions normally performed by the second secondary processor are performed by the first secondary processor, wherein a division of workload increases performance of the data processing system. This architecture allows shifting of workload down to the secondary bus.

Abstract: Provided is a method of forming a silicide layer on the top and sidewall surfaces of a polysilicon gate/interconnect in a MOS transistor and on the exposed surfaces of the source and drain regions of the transistor. Devices produced according to the present invention may have different types of silicide formed on their gate and their source/drain electrodes. The invention achieves the advantages of silicide encapsulation of a polysilicon gate in an MOS transistor while also providing silicidation of the source/drain regions of the transistor, thereby reducing electrode resistivity in the transistor and interconnect.

Abstract: A clock and data recovery circuit for use in a serial data communications channel includes two phase-locked loops, the two PLLs being coupled together through the use of a matched pair of voltage controlled oscillators. Each of the matched pair of oscillators includes both coarse and fine adjustment inputs. The first loop generates a first frequency based upon a reference clock input and provides a coarse tuning signal, based on the first frequency, to the second loop circuit. The second VCO drives the second loop circuit at the same frequency as the first circuit, while the second circuit is also coupled to the incoming data stream so as to provide the fine adjustment input to the second VCO. In this way, the second VCO, i.e., the second loop, is synchronized to the data, yet it remains synchronized to the reference frequency even during relatively long periods of time during which transitions in the data stream are infrequent.

Abstract: A reconstruction filter is described. An input is configured to receive an output signal from a digital to analog converter. An input sampling circuit is operative to store a sample of the output signal from the digital to analog converter. An input pulse generating switch that generates a pulse, the energy of the pulse being determined by the sample of the output signal from the digital to analog converter. An amplifier receives the pulse at an amplifier input and provides an output signal at an amplifier output so that an output signal is produced that reduces distortion caused by imperfections in digital to analog converter.

Abstract: A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; high level what-if analysis; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure. The methodology includes using estimators for partitioning and evaluating a design prior to logic synthesis.

Abstract: A system and method for managing data stored in a cache block in a cache memory includes a cache block is located at a cache block address in the cache memory, and the data in the cache block corresponds to a storage location in a storage array identified by a storage location identifier. A storage processor accesses the cache block in the cache memory and provides a cache management command to a command processor. A processor memory coupled to the storage processor stores a search key based on the storage location identifier corresponding to the cache block. A command processor coupled to the storage processor receives a cache management command specified by the storage processor and transfers the storage location identifier from the processor memory. A cache management memory stores a cache management structure including the cache block address and the search key.

Abstract: A system for designing integrated circuits that use frequency synthesizers to ensure testability. A testability circuit is added or connected to the frequency synthesizer that will receive allow the integrated circuit to operate in a system mode for normal function and in a test mode during testing. In the test mode, the testability circuit will inhibit the reset signal from initializing the integrated circuit until the frequency synthesizer has reached phase lock. The testability circuit may be implemented as a component in the frequency synthesizer cell in an ASIC design system such that anytime the frequency synthesizer is used, the integrated circuit is testable.