Abstract: An analog-to-digital (A/D) converter for converting an analog signal into a digital signal includes a first resistor ladder coupled between a first reference voltage and a second reference voltage. The A/D converter also includes a second resistor ladder that matches the first resistor ladder and that has a first end and a second end coupled to an analog signal source. The first resistor ladder and the second resistor ladder are coupled to at least two comparators with each comparator having a reference input and an analog input. The impedance at each reference input due to the first resistor ladder matches the impedance at each corresponding analog input due to the second resistor ladder.

Abstract: A combinational logic circuit for determining whether an address is inside or outside a range at least partially defined by a control address bit. The logic circuit includes combinational logic connected to an address bit line for receiving the address bit being tested and connected to a control address bit line for receiving the control address bit at least partially defining the range. The combinational logic is configured to produce a signal indicating whether the address bit being tested and the control address bit at least partially defining the range are equal. The combinational logic is also configured to produce a signal representing a mathematical relation between the address bit being tested and the control address bit at least partially defining the range. The mathematical relation identifies whether the address bit being tested is inside or outside the range at least partially defined by the control address bit.

Abstract: A method for treating exposed surfaces of a low k carbon doped silicon oxide dielectric material in order to protect the low k carbon doped silicon oxide dielectric material from damage during removal of photoresist mask materials is described. The process comprises (a) first treating the exposed surfaces of a low k carbon doped silicon oxide dielectric material with a plasma capable of forming a densified layer on and adjacent the exposed surfaces of low k carbon doped silicon oxide dielectric material and (b) then treating the semiconductor wafer with a mild oxidizing agent capable of removing photoresist materials from the semiconductor wafer. These steps will prevent the degradation of the exposed surfaces of a low k carbon doped silicon oxide dielectric material during removal of an etch mask after formation of vias or contact openings in the low k carbon doped silicon oxide dielectric material.

Abstract: An electronic circuit coordinates accesses to a register shared among multiple system resources by managing the priority of each system resource relative to others. When a priority register access is initiated, a signal is generated to block a simultaneous or overlapping register access by another system resource. If another register access is already in operation, it will be completed before the priority register access operates on the shared register. Otherwise, if the priority register access operates on the register first, the non-priority register access is held off until the priority register access completes. A method coordinates the potentially simultaneous or overlapping register accesses by multiple system resources to a shared register. When a priority register access initiates, a lookahead signal issues to set a busy flag that blocks competing register accesses until the priority register access completes.

Abstract: To reduce FIFO access cycles across a system bus in a multi-processor system in which two processors communicate across a system bus through a FIFO, two separate FIFO descriptors are provided. The first descriptor is maintained by the processor located on-board with the FIFO, and the second descriptor is maintained by an off-board processor which communicates with the FIFO across the bus. When one processor performs a FIFO operation, the processor updates the other processor's descriptor via a memory access across the bus. Additionally, one module passes credits to the other to indicate that the latter has permission to perform a plurality of FIFO operations consecutively. In one embodiment a special non-valid data value is used to indicate an empty FIFO position.

Abstract: In a data processing system having few initiators or several initiators with the same parameters, support for all initiators is provided by storing sets of parameters and corresponding lists of initiator IDs in cache entries. Based on the initiator ID in a selection command, the target selects the appropriate parameters and automatically transitions to data transfer mode. Low cost support for all initiators is thus provided.

Abstract: A wireless communication unit for a wireless communication system transmits and receives video, audio and data signals within an RF bandwidth. The RF bandwidth is allocated among the video, audio and data signals to allow the video, audio and data signals to fit within the RF bandwidth. The allocation is performed by buffering the signals, making priority assignments to each of the buffered signals, and transmitting the buffered signals according to the priority assignments. The transmitted signals occupy the RF bandwidth in portions specified by the priority assignments. The priority assignments can be changed during a communication link. The subscriber unit receives a transmission header from another party on the communication link, which may include a request by the other party to change the priority assignments. If such a request is received, the subscriber unit automatically changes the priority assignments in response to the request.

Abstract: Disclosed is the formation of additional lines, either dummy lines or active lines, in an electrically conductive pattern of lines to provide more uniform loading for either etching or chemical/mechanical polishing of a layer of electrically conductive material from which the pattern of lines is formed. Also disclosed is the use of additional or dummy vias to balance the loading during etching of the vias, as well as to provide stress relief for underlying metal in regions or areas having a low density of vias. Further disclosed is the use of a working grid on the integrated circuit structure to analyze the spacing of lines or vias for the above effects.

Abstract: A reference voltage generator for producing a regulated, temperature-compensated output voltage from an unregulated power supply voltage is provided herein. The reference voltage generator includes a pre-regulating circuit and a temperature-compensating circuit. The temperature compensating circuit includes a first series path comprising a first cascode current sources and a first resistor; a second series path comprising a second cascode current source, a first field effect transistor and a first diode; and a third series path comprising a third cascode current source, a second field effect transistor, a second resistor and a second diode. The first series path being connected to the second series path between the first field resistor and the first diode.

Abstract: A power bus grid architecture for an integrated circuit including a plurality of main bars assembled along the perimeter of the grid and a plurality of bus bars assembled within the perimeter of the grid. The bus bars are each composed of a plurality of segments with each segment having a substantially constant width. Each segment on certain bus bars has a different width from the next adjacent segment. The width of a particular segment is determined by the distance of the segment from the nearest main power bar. Because the current flow through the segments nearest to the main power bar tends to be greater than the current flow through the segments further from the main power bar, the segments nearest to the main power bar can be made much wider than the segments furthest from the main power bar without significant deleterious effects to the circuit from voltage drops or electromigration.

Abstract: An apparatus is presented which gathers information about optical disks (e.g., CDs) stored in an optical disk player and provides this information to a user. The apparatus includes the optical disk player and a computer system coupled to the optical disk player. The optical disk player retrieves data from optical disks, and includes storage for multiple optical disks (i.e. an optical disk cassette). A data transfer unit within the optical disk player transfers information about the contents of one or more optical disks in the cassette to the computer system. The computer system includes a memory unit for storing the information. The memory unit includes system software for controlling the transfer of the information from the optical disk player to the computer system, and for controlling the storing of the information within the memory unit. The computer system may also include a monitor for displaying the information.

Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the cells. Designing of the IC's require meeting real-world constraints one of which is the performance of the IC, or the period of time required by the integrated circuit to produce the output signals from the time the input signals are available. Typically, the performance of an integrated circuit is determined by the slowest path of the signals, called the critical path. The critical path is usually only a small portion of the IC. The present invention discloses a method and apparatus for transforming the circuits comprising the critical path, thereby increasing the performance of the entire IC. The transformation is performed by segmenting, or blocking, the cells which make up the critical path. Then, each block is transformed, or replaced, with a resynthesized circuit to which both the digital 0 and digital 1 values are provided.

Abstract: A system and method are presented for forming a grid array device package around an integrated circuit (i.e., chip). The device package includes a substrate, a stiffener, a heat spreader, and an optional heat sink. The chip includes multiple I/O pads arranged upon an underside surface. The substrate includes a first set of bonding pads on an upper surface configured to vertically align with the I/O pads. The chip is connected to the first set of bonding pads using the C4 method. The stiffener, a rigid member able to retain its shape during C4 heating, may be attached to the upper surface of the substrate prior to the C4 process, helping the substrate maintain its planarity during and after the C4 process. The stiffener has an opening dimensioned to receive the chip and exposing the first set of bonding pads. Following the C4 process, a first space between the underside surface of the chip and the upper surface of the substrate is filled with an underfill material.

Abstract: An audio decoder which includes a coefficient memory and an arithmetic logic unit (ALU) can implement an efficient method for calculating a gain value specified by a range control field. In one embodiment, the audio decoder comprises coefficient memory, an ALU, frame control logic, and ALU control logic. The frame control logic extracts a range control field value from an audio packet header and provides it to the ALU control logic. The ALU control logic takes the binary representation of the range control field value and uses it to provide a sequence of addresses to the coefficient memory. In response to the sequence of addresses, the coefficient memory provides a sequence of pre-calculated factors to the ALU. The ALU control logic further directs the ALU to determine the product of the pre-calculated factors in the sequence. As a final step in finding the gain value, the ALU control logic may provide a shift instruction to the ALU.

Abstract: A method of electroplating a high density integrated circuit (IC) substrate using a conductive elastomer including the steps of providing an IC substrate made of nonconductive material having a plurality of conductive traces with conductive trace lands formed on its surface. Covering only the traces (not the trace lands) with a plating resist and exposing portions of the conductive traces. Inserting the IC substrate into a electroplating fixture. Engaging a conductive elastomer to the IC substrate, covering the plurality of conductive traces and electrically connecting all of the traces together. Electroplating the trace lands on the IC substrate with conductive material (such as gold or nickel) by using the conductive elastomer as the electrical connection to the trace lands (via the exposed metal traces). Disengaging the conductive elastomer after electroplating is finished and removing the IC substrate from the electroplating fixture.

Abstract: Methods and associated apparatus for balancing the I/O request processing load within a plurality of controllers in a storage subsystem. The methods of the present invention are operable within interconnected controllers of a storage subsystem to shift the processing of received I/O requests to less loaded controllers and to do so in a manner transparent to legacy attached host systems. In a first embodiment of the present invention referred to as back-end load balancing, I/O requests are transferred from a first controller, to which the I/O request was directed by the attached host system, to a second controller for further processing. In this back-end load balancing embodiment, all write data associated with a write request as well as returned information including status or read data, is exchanged between the first and second controllers such that the first controller performs all communication with the attached host system.

Abstract: Data and strobe comparators are provided wherein each comparator includes a wide-swing bias circuit, an input stage, a current bias circuit, a load circuit, an output buffer and a clamp circuit. The wide-swing bias circuit, input stage, current bias circuit, load circuit, and a clamp circuit comprise a well-controlled preamplifier circuit. The input stage includes low-threshold transistors that receive differential inputs. The transistors form a single stage input. The low-threshold transistors turn on at several hundred millivolts, and from an operational perspective, almost immediately. The well-controlled aspect of preamplifier is achieved since all the transistors are made from the same semiconductor manufacturing process and have their physical dimensions precisely matched. An output buffer is connected to the preamplifier. Such a buffer is used for both data and strobe reception. The buffer includes a differential-to-single-ended converter that includes low-threshold transistors.

Abstract: An audio decoder converts a linear PCM audio data packet into two concurrently provided digital audio sample sequences: a high-quality sequence and a decimated sequence. In one embodiment, the audio decoder is part of an audio system that further includes two audio devices. The first audio device is configured to produce an audio signal from a 96 kHz sequence, and the second audio device expects a 48 kHz sequence. The audio decoder includes an input interface, an arithmetic logic unit (ALU), and two output buffers. The input interface is configured to receive a linear PCM audio data packet and to reconfigure bytes as necessary to reconstruct a sequence of unscaled audio samples. The ALU multiplies each of the unscaled audio samples by a gain factor and buffers the resulting scaled audio sample sequence in a first output buffer.

Abstract: A ROM for storing constants used in both the MPEG-2 and AC-3 audio decoding algorithms. These constants include (i) matrixing constants for AC-3 and MPEG audio decoding algorithms and (ii) windowing coefficients for AC-3 and MPEG audio decoding algorithms. The ROM includes (a) a first partition for storing a first set of constants which are windowing coefficients for AC-3 decoding, (b) a second partition for storing a second set of constants which are constants used for pre-IFFT and post-IFFT steps of AC-3 decoding (Blkswflag=1), (c) a third partition for storing a third set of constants which are both IDCT coefficients for MPEG decoding and IFFT coefficients for AC-3 decoding, (d) a fourth partition for storing a fourth set of constants which are constants used for pre-IFFT and post-IFFT steps of AC-3 decoding (Blkswflag=0), and (e) a fifth partition for storing a fifth set of constants which are windowing coefficients for MPEG decoding.

Abstract: Several hybrid CMOS circuit configurations that include both static CMOS logic and Domino CMOS logic are described. Each circuit configuration includes two registers that surround the Domino logic to allow that logic to be tested. One of the registers receives an input test vector that can either be loaded directly through a primary set of inputs or by a serial scan chain if the inputs to the register are not directly accessible. The second register is used to latch the results of the test vector application. The contents of this register can then either be read directly through a primary set of outputs if there is no static CMOS logic between the outputs of the register and a primary set of outputs of the circuit, or scanned out of the second register using a serial scan chain. A Domino scan flip-flop is also described that produces significant transistor count reduction over conventional static scan flip-flops.