Abstract: Gaseous reactants capable of depositing a thin film on a semiconductor substrate are introduced into a deposition zone of a deposition apparatus through a gaseous reactants dispersion apparatus having rounded corners and smoothed anodized surfaces and maintained at a temperature ranging from about 70.degree. C. to about 85.degree. C., and preferably from about 75.degree. C. to about 80.degree. C., to inhibit the deposition and accumulation on such surfaces of charged materials capable of generating particles which may cause damage to the semiconductor substrate.

Abstract: Apparatus and an associated method calculates a CRC remainder for a block of data, such as a block of data retrieved from a CD-ROM device. CRC calculations are performed to provide assurances of data integrity subsequent to error corrections of the block of data. CRC remainders associated with N powers of two are stored in the look-up table. When calculating the CRC remainder, selected values stored in the look-up table are retrieved and combined to form the CRC remainder for the block of data.

Abstract: A semiconductor package is disclosed. According to one embodiment, the package comprises a substrate having a top surface with traces thereon and a bottom surface with solder balls thereon, the substrate comprising at least three material layers defining at least four substantially planar metal layers, wherein one of the metal layers comprises a reference layer that serves as a reference to both traces on a metal layer above the reference layer and traces on a metal layer below the reference layer. A semiconductor die is mounted to the substrate and bonding wires electrically connect the semiconductor die to the traces on the top surface of the substrate. The traces on the top surface of the substrate are electrically connect to the solder balls through vias and possibly through routing on another metal layer.

Abstract: An audio decoder is provided with a programmable and re-configurable downmixing process. In one embodiment, the audio decoder includes a control module and a data path. The data path is configured to read, scale, add, and write audio samples to and from various audio channel frame buffers. The control module implements state diagrams which specify various control signals for directing the operations of the data path. The control module implements state diagrams for directing windowing and downmixing operations. The order in which these operations are performed may be reconfigurable, i.e. downmixing may be performed before or after windowing. This reconfigurability advantageously permits the system designer to trade a slight audio quality enhancement for a decreased memory requirement for some speaker configurations. The downmixing operation requires scaling coefficients which are provided by the control module.

Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that placement of the cell and the wire routine be done correctly to avoid any congestion of wires. Placement of the cells and the routing of the wires to avoid congestion can be accomplished by determining congestion of various regions, or pieces, of the IC's after an initial placement of the cells and routing of the wires. The present invention discloses a method and apparatus to define the regions, or pieces, of the IC, determine various density measurement of the pieces, and adjust the sizes of the pieces to reduce congestion of congested pieces by reallocating space from uncongested pieces to congested pieces.

Abstract: A flat panel display is coupled with an electrostatic stylus driven digitizing panel to produce a display and digitizer system having an interference control feature. The interference control feature first determines the operating frequency of the flat panel display and/or the operating frequency of the stylus. The interference controller may then incrementally reduce the operating frequency of the flat panel display and/or the operating frequency of the stylus until the operating frequency causing the least interference is ascertained. Once the operating frequency causing the least interference is ascertained the interference controller selects new operating parameters for the display and digitizer system.

Abstract: A user control system for allowing an end user to control the level of a signal transmitted from a host to a transmission medium is disclosed. The user control system includes a digital current controller electrically connected to a bias voltage generator, and formed of a binary weighted transistor array that is switched according to user inputs received from a host. Also disclosed is a transmission system incorporating the user control system and further including a current-mode digital-analog converter, an on-chip low-pass filter, a line driver, and output impedance control. Further, a method for optimizing the output signal through user control is disclosed. The control system and method can be used in transmission of Ethernet signals onto an unshielded twisted pair cable. In addition, with appropriate modification, the transmission system and method can be used for transmitting ATM or other signals onto a transmission medium.

Abstract: Process monitoring circuitry according to the invention incorporates additional routing structures that approximate signal delays due to long metal routing paths. The additional process monitor circuitry builds upon existing approaches without increasing the die size of an integrated circuit through the utilization of excess silicon space available between the bonding pads and the scribe lines of an integrated circuit wafer. More specifically, supplemental metal routing lines and vias are included in the delay paths of process monitor circuitry and located on the integrated circuit such that impact to other metal signal lines/vias used in the actual design is minimized. The supplemental metal routing lines are disposed in unused routable silicon space, such that no silicon area penalty is suffered as a result of having long metal routing lines.

Abstract: An optimized translation lookaside buffer (TLB) utilizes a least-recently-used algorithm for determining the replacement of virtual-to-physical memory translation entries. The TLB is faster and requires less chip area for fabrication. In addition to speed and size, the TLB is also optimized since many characteristics of the TLB may be changed without significantly changing the overall layout of the TLB. A TLB generating program may thus be used as a design aid. The translation lookaside buffer includes a level decoding circuit which allows masking of a variable number of the bits of a virtual address when it is compared to values stored within the TLB. The masking technique may be used for indicating a TLB hit or miss of a virtual address to be translated, and may also be used for invalidating selected entries within the TLB.

Abstract: The invention provides a method and system for correcting imbalance in in-phase and quadrature components of a modulated received signal. The method includes assuming a signal imbalance to exist in the received signal, the signal imbalance having an amplitude imbalance and a phase imbalance, generating an amplitude imbalance correction factor and a phase imbalance correction factor to lessen the signal imbalance, and re-evaluating the amplitude and phase imbalance correction factors over a set of readings of the in-phase and quadrature components until the signal imbalance is minimized.

Abstract: An apparatus for use in the deposition of oxide on a wafer, the apparatus including a chamber for receiving oxygen gas that is used for forming the oxide on the wafer, the apparatus comprising: a wafer chuck located within the chamber, the wafer chuck capable of supporting the wafer during the deposition of oxide on the wafer; and an oxide blocking member located within the chamber and detached from the wafer, the oxide blocking member capable of preventing the deposition of oxide in at least one predetermined area of the wafer.

Abstract: An audio decoder is provided with a programmable and re-configurable downmixing process. In one embodiment, the audio decoder includes a control module and a data path. The data path is configured to read, scale, add, and write audio samples to and from various audio channel frame buffers. The control module implements state diagrams which specify various control signals for directing the operations of the data path. The control module implements state diagrams for directing windowing and downmixing operations. The order in which these operations are performed may be reconfigurable, i.e. downmixing may be performed before or after windowing. This reconfigurability advantageously permits the system designer to trade a slight audio quality enhancement for a decreased memory requirement for some speaker configurations. The downmixing operation requires scaling coefficients which are provided by the control module.

Abstract: A multiple channel data communication buffer includes a first side having a plurality of communication ports and a second side having data routing port. A single port transmit memory is coupled between the plurality of communication ports and the data routing port. A transmit arbitration circuit is coupled to the single port transmit memory, which arbitrates access by the plurality of communication ports and the data routing port to the single port transmit memory. A single port receive memory is coupled between the plurality of communication ports and the data routing port. A receive arbitration circuit coupled to the single port receive memory, which arbitrates access by the plurality of communication ports and the data routing port to the single port receive memory.

Abstract: A thermally stable inter-metal dielectric for interlayer dielectric material has enhanced adhesiveness by introduction of an adhesive material. The adhesive material may reside only at the interface of the inter-metal dielectric or interlayer dielectric with adjacent metalization and polysilicon layers. A disclosed thermally stable intermetal dielectric is a fluorinated polymer such as polyfluoropyreline. A disclosed adhesive material is a highly polar material such as a thiofluorocarbon. These materials may be deposited by chemical vapor deposition by first activating fluoropyreline monomer and di(thiodifluoromethane) in a heated activation chamber to convert them to a form suitably reactive to form a polymeric dielectric on a wafer surface.

Abstract: A system and method for decoding an MPEG video bitstream comprises, comprising a macroblock core (MBCORE) which processes video bitstream data and computes discrete cosine transform data and a parser which parses the video bitstream macroblocks into multiple data blocks used in subsequent stages of decoding. fixed length data words comprising variable length objects using a novel rotating register arrangement. A multistage transformation/motion compensation core (TMCCORE) uses intermediate memory. The IDCT first stage has the ability to operate on a first data block while the second stage simultaneously operates on a second data block. The TMCCORE receives the discrete cosine transform data from the MBCORE and calculates and reconstructs a frame therefrom using motion compensation. The MBCORE can operate on data from a first macroblock while the TMCCORE simultaneously operates on data from a second macroblock.

Abstract: The present invention provides a digital clock recovery circuit, which includes a frequency synthesizer generating a number of clock phase signals. The digital clock recovery circuit also includes a phase interpolation unit, which interpolates the clock phase signals from the frequency synthesizer to increase the number of clock phase signals. Additionally, the digital clock recovery circuit also includes a phase detector, a digital filter, and a phase selection unit. The phase detector has an output connected to a digital filter, which is connected to the phase selection unit. The phase detector sends signals filtered through the digital filter to select clock phase signals input into the phase selection unit from the phase interpolation unit. The output of the phase selector provides the recovered clock signal and also connected to the input phase detector.

Abstract: A method of planarizing a semiconductor wafer to a distance from a semiconductor substrate of the wafer is disclosed. The method includes the step of forming in the wafer a metallic reporting substance that is at the predetermined distance from the substrate of the wafer. The method also includes the step of polishing a first side of the wafer in order to remove material from the wafer. The method further includes the step of utilizing an atomic absorption spectroscopic technique to detect the presence of the metallic reporting substance in the material removed from the wafer. Moreover, the method includes the step of terminating the polishing step in response to the detection of the metallic reporting substance. An associated apparatus for polishing a semiconductor wafer down to a metallic reporting substance of the wafer is also described.

Abstract: A corrosion inhibiting cleaning process for removing etch-residue from an integrated circuit substrate is described. The corrosion inhibiting cleaning process includes: (1) obtaining an integrated circuit substrate that has undergone etching; and (2) cleaning the integrated circuit substrate using a post-etch cleaning solution including a corrosion inhibiting agent in a sufficient concentration to effectively inhibit corrosion of the integrated circuit substrate.

Abstract: A static random-access memory integrated circuit formed on a single substrate includes a storage IGFET formed on the substrate and having a first area and a first capacitance. A gating FET formed on the substrate has an area substantially equal to the first area with a capacitance substantially less than the first capacitance. In one aspect, the storage FET has a substantially thicker gate oxide than the gating FET. In another aspect, the gate oxide of one of the FETs is formed from a different material than that of the other FET. A method for fabricating such IGFETs on a single substrate is also provided in which source and drain regions are formed adjacent the surface of the substrate. A first layer of gate oxide is formed on the surface of the substrate over the channels of the first and the second FETs. The first layer of gate oxide is then covered by a nitride layer which is thereafter etched away over the channel of one of the FETs.

Abstract: A system and method for synchronizing a decoded, interlaced-field data stream with an interlaced field display. A system for displaying an MPEG encoded data stream includes an MPEG decoder which converts the encoded data stream into a sequence of frames. Each frame has an associated top field, bottom field, top-field-first flag, and repeat-first-field flag. The system also includes a display processor which receives the flags and determines a field display sequence for each frame which conforms to an overall display sequence which strictly alternates between top and bottom fields. This strict alternation in enforced even when the decoded field sequence does not adhere to a strict alternation. The system achieves this result with a worst-case temporal distortion of one field by inserting or omitting a 3:2 pulldown frame at each broken alternation point.