Abstract: A corrosion inhibiting cleaning process for removing etch-residue from an integrated circuit substrate is described. The corrosion inhibiting cleaning process includes: (1) obtaining an integrated circuit substrate that has undergone etching; and (2) cleaning the integrated circuit substrate using a post-etch cleaning solution including a corrosion inhibiting agent in a sufficient concentration to effectively inhibit corrosion of the integrated circuit substrate.

Abstract: An integrated circuit I/O buffer has an output driver. The output driver includes first, second and third voltage supply terminals and a pad terminal. A pad pull-up transistor is coupled in series between the first voltage supply terminal and the pad terminal and has a pull-up control terminal. A pad pull-down transistor is coupled in series between the second voltage supply terminal and the pad terminal and has a pull-down control terminal. A voltage protection transistor is coupled between the pad terminal and the pad pull-down transistor. The voltage protection transistor has a control terminal and a capacitance between the control terminal and the pad terminal. A resistor is coupled in series between the control terminal of the voltage protection transistor and the third voltage supply terminal and forms a resistor-capacitor (RC) circuit with the capacitance.

Abstract: A method of planarizing a semiconductor wafer having a polishing endpoint layer that includes a ligand is disclosed. One step of the method includes polishing a first side of the wafer in order to remove the ligand from the wafer. Another step of the method includes determining that a chelating agent has bound the ligand due to the polishing step removing the ligand of the polishing endpoint layer. The method also includes the step of terminating the polishing step in response to determining that the chelating agent has bound the ligand. A polishing system is also disclosed which detects a polishing endpoint based upon a chelating agent binding a ligand of a polishing endpoint layer of a semiconductor device.

Abstract: A multimedia decoder is provided with an audio decoder bypass module for forwarding undecoded audio bitstreams directly to external system components. In one embodiment, the multimedia decoder includes an audio decoder, and a bypass module. The audio decoder operates on the data in an audio bitstream buffer to convert at least a portion of the audio bitstream into a set of digital audio signals. The bypass module is configured to provide the full information content of the audio bitstream to an external system component which may be able to convert a greater portion of the audio bitstream into a second set of digital audio signals. As the audio decoder and bypass module each retrieve data from the audio bitstream buffer, they each use a pointer to track which location of the buffer to access next.

Abstract: Provided is a semiconductor flip chip die metal layout which provides a flat UBM where surface metal pads are narrower than UBMs in order to accommodate decreased die pitch. This is achieved by depositing a metal region adjacent to and closely spaced from the pad which, together with the pad, is capable of providing a substrate that will result in a substantially flat passivation layer surface on which the UBM is subsequently deposited. The adjacent closely spaced metal region may be provided by bringing metal traces closer to a reduced size surface metal pad (into the die surface area underlying the UBM), and/or by depositing dummy metal similarly near the pad. The dummy metal may also be deposited over the whole chip surface area not occupied by other electrical components.

Abstract: An audio decoder is described which supports simple sound-effect generation. The audio decoder includes a direct access pulse code modulation (PCM) first-in-first-out buffer (FIFO) to support simple sound effect generation. In one embodiment, the audio decoder additionally includes an input buffer, a decoding module, and an output interface. The input buffer buffers incoming data frames for the decoding module to retrieve and convert to a sequence of decoded audio samples. The FIFO is configured to receive and buffer audio sound effect samples from a control component external to the audio decoder. The output interface is configurable to retrieve decoded audio samples from the decoding module and audio sound effect samples from the FIFO. Any retrieved audio sound effect samples are included in a digital audio output signal provided by the output interface. The digital audio output signal may be provided directly to a digital-to-analog converter for sound reproduction.

Abstract: A subscriber station for decrypting and decompressing data is provided on a single chip. The chip includes a DES decryption unit for performing decryption of incoming data with a DES key, a public key decryption unit for decrypting the DES key, a general purpose microprocessor for performing decompression, and a Secure Buffer for protecting the decrypted data prior to decompression. The chip includes an embedded key for the public key decryption unit and a bus for providing a data communication path between the microprocessor and the decryption units.

Abstract: An apparatus and method are presented for testing an adhesive layer formed between an integrated circuit and a plate, wherein the plate may be semiconductor device package substrate or a heat spreader. The apparatus includes a pull stud and a pull arm. The pull stud has an upper portion and a lower portion, wherein the lower portion is attached to a surface of the integrated circuit opposite the plate. The upper portion of the pull stud may be, for example, a tapered cylinder having a large end and a small end. The small end meets the lower portion of the pull stud. The pull arm has two opposed ends and at least one bracket for receiving a force. One of the pull arm ends has a "V"-shaped opening surrounded by a lip which receives the upper portion of the pull stud. During use, the lip contacts and retains the upper portion of the pull stud. The opening has an upper wall, and an upper surface of the pull stud contacts the upper wall when the upper portion of the pull stud is inserted into the opening.

Abstract: A method for maintaining login service parameters includes a step of allocating space for and storing a login service parameter portion of a logged in port. A login service parameter of a logged in port is then compared with stored login service parameter structures. If the login service parameter of the logged in port, except for a login service parameter portion thereof, is identical with one of the stored login service parameters, a step of adding a first pointer to that stored login service parameters structure into the stored login service parameter portion structure is carried out. A new login service parameter portion structure is allocated and the process repeated, thereby creating a linked list of login service parameter portion structures, each login service parameter portion structure pointing to both the stored login service parameter structure and to a next login service parameter portion structure.

Abstract: A misregistration fidutial structure and method for verifying registration between multiple layers of multi-layer subassembly for an electronic device. A substrate for the subassembly is provided, where a first layer, typically having electrically conductive signal paths, is placed over the substrate. A second layer, typically a soldermask, is placed over the first layer. An aperture is formed in the second layer a predetermined horizontal distance from a conductive signal path in the underlying first layer so that through visual observation one can easily determine whether misregistration is present when any portion of the underlying signal conductive path is observable through the second layer aperture.

Abstract: A modular state machine, and associated method permits reuse of modular portions of the state machine. Instead of duplicating identical groups of states of the state machine, jumps are provided to a modular portion of the state machine formed of a group of states. The circuit area required to implement the state machine is thereby reduced.

Abstract: An integrated circuit residing within a die includes at least two columns of circuits separated by a routing space. A buffer is formed within the integrated circuit for transferring signals between the integrated circuit and a location remote from the die. At least one portion of the buffer is formed as a buffer circuit column, where the buffer circuit column is aligned with a column of circuits within the integrated circuit but outside of the buffer.

Abstract: A precise timing delay method and apparatus. A phase-locked loop (PLL) in combination with a timing reference is used to calibrate a precise delay. These delays are then duplicated throughout the chip and controlled by the same current as in the PLL. This makes the delays process, voltage, and temperature insensitive. The delays can be programmed by selecting the desired delay through a multiplexer. Providing high precision delays are particularly advantageous for use in devices such as computer bus isolators.

Abstract: A process for modifying an alignment mark is described. The process includes: (i) fabricating the alignment mark on an integrated circuit substrate surface, which alignment mark includes an alignment mark fill material of defined composition; and (ii) introducing a step in the alignment mark by polishing the integrated circuit substrate surface and removing at least some of the alignment mark fill material from the integrated circuit substrate to form a modified alignment mark. The modified alignment mark is capable of allowing an alignment tool to detect the modified alignment mark when the modified alignment mark is covered by an opaque layer and thereby align a first layer of the integrated circuit substrate to the opaque layer that is disposed above the first layer.

Abstract: A thermally-enhanced flip chip integrated circuit (IC) package has a package substrate to which an IC die is bonded. A thermally-conductive heatspreader, having planar dimensions larger than the IC die, is thermally bonded at or near its center to an upper surface of the IC die. A plurality of cooling extensions are formed that protrude from a lower surface (the surface closest to the package substrate) of the heatspreader so as to create passageways through which cooling air may flow. In one embodiment, the cooling extensions are parallel fins that protrude transversely from the lower surface of the heatspreader, thereby forming U-shaped channels. In another embodiment, the cooling extensions are an array of fin pins that protrude transversely from the lower surface of the heatspreader.

Abstract: The present invention provides a method for forming an electrostatic chuck. A chuck body is provided in which the chuck body includes an insulating layer. Metal is implanted into a surface of the chuck body, wherein a conductive layer of metal is formed within the insulating layer of the chuck body.

Abstract: In one embodiment, a method of forming a barrier layer for contacting a metal interconnect layer to one or more exposed N and P type silicon regions on a wafer. The wafer is heated with a direct radiation source, such as a lamp. To equalize the differing emissivities of the N type and P type silicon regions, an opaque layer of refractory metal is first formed on the regions at a temperature below approximately 100.degree. C. A refractory metal deposition process is then conducted at temperatures between 230.degree. C.-425.degree. C. During this higher temperature deposition process, the reducing gas is ramped up with time to increase the deposition rate of the refractory metal as the exothermic reducing reactions increasingly heat the contact areas.

Abstract: The present invention relates to a semiconductor device, preferably a capacitor, and a method of forming the same. The method adds only a single additional masking step to the fabrication process and reduces problems relating to alignment of various layers. A relatively thick insulation layer is formed over a bottom electrode. An opening having a sidewall that is etched in the insulation layer using a mask to expose a portion of the bottom electrode. Once the mask is removed, a dielectric layer and conductive layer are then sequentially deposited over the entire structure, including sidewalls. Thereafter, chemical-mechanical polishing is used to remove portions of the conductive layer and the dielectric layer so that the conductive layer and dielectric layer which remains forms, for example, the top electrode and dielectric layer of the integrated circuit capacitor.

Abstract: A method and system for converting computer peripheral equipment to SCSI-compliant devices includes an interface controller which converts a mass storage device communicating on an ATA interface to a target device communicating in SCSI commands across an IEEE-1394 interface. The controller converts SCSI commands in CDBs in the IEEE-1394 ORBs to ATA ORBs and then directly to ATA/ATAPI commands, through a mapping function.

Abstract: One aspect of the invention relates to a semiconductor substrate. In one version of the invention, a semiconductor substrate includes a package substrate having first and second surfaces with conductive traces formed thereon and structures for providing electrical connection between selected conductive traces, a die attach area on the first surface of the package substrate adapted to provide physical connection to a semiconductor die, the die attach area having conductive contacts for providing electrical connection between the die and conductive traces on the first surface, a package frame, at least one substrate strap which connects the package substrate to the package frame, the substrate strap being formed integrally with the package substrate and the package frame.