Abstract: An automated endpoint detection process for detecting residual metal on a surface of an integrated circuit substrate after subjecting said surface to a chemical-mechanical polishing process is described. The process includes obtaining a baseline reflected radiation signal for a surface on a standard integrated circuit substrate surface that is substantially free of residual metal, directing radiation generated from a radiation source on at least a portion of the surface of the integrated circuit substrate, detecting a resulting reflected radiation signal from the surface of the integrated circuit substrate and comparing the reflected radiation signal to the baseline reflected radiation signal and thereby determining whether residual metal is present on the surface of the integrated circuit substrate.

Abstract: A method of preserving signal integrity of buses is disclosed. One step of the method includes the step of forming between a first bus and a first bus port of a bus controller, a first stub that is no greater than a first maximum stub length allowed for the first bus by terminating the first bus with a first terminating circuit if (i) the first bus port does not have at least one device coupled thereto, and (ii) a second bus port of the bus controller does have at least one device coupled thereto. The method also includes the step of forming between the first bus and a second bus port of the bus controller, a second stub that is no greater than the first maximum stub length allowed by terminating the first bus with a second terminating circuit if (i) the first bus port does have at least one device coupled thereto, and (ii) the second bus port does not have at least one device coupled thereto. Apparatus for implementing the method are also disclosed.

Abstract: An end effector to facilitate conditioning a surface of a polishing pad used in chemical-mechanical polishing of a substrate surface is described. The end effector includes an inwardly recessing contact surface capable of attaching to a conditioning disk having a conditioning surface such that the conditioning surface conforms to a substantial portion of the polishing pad, which protrudes outwardly under operation and thereby effectively conditions a substantial portion of the polishing pad. The present invention also describes a conditioning disk for effectively conditioning a surface of a polishing pad used in chemical-mechanical polishing of a substrate surface. The conditioning disk includes (i) a second surface capable of attaching to a contact surface of an end effector and (ii) an inwardly recessing conditioning surface that conforms to a substantial portion of said polishing pad, which protrudes outwardly under operation, and thereby effectively conditions the polishing pad.

Abstract: A method for improving the accuracy of quiescent current estimation for integrated circuits. When used with a CMOS process, the method involves selecting transistors having a polysilicon gate length corresponding to the minimum length permitted by process design rules. For each of the selected transistors, the intersection of the width of the polysilicon gate and the active area of the transistor is calculated. The widths of all of the selected minimum length devices are summed to generate a total width dimension value. The total width dimension value is multiplied by a predetermined quiescent current per unit width conversion value to produce an estimate of the quiescent current drawn by the integrated circuit. In an alternate embodiment of the invention, the total width dimension value is multiplied by a range of predetermined quiescent/leakage current per unit width values representing a range of testing conditions and temperatures.

Abstract: A data communication circuit buffers data between a shared resource and a plurality of data communication interfaces through a plurality of respective first-in-first-out ("FIFO") buffers. The data is divided into multiple-bit data frames having a start and an end. The circuit maintains a priority level for each FIFO buffer and initializes the priority level of each FIFO buffer to a first priority level. The circuit passes bits of the multiple-bit data frames from the shared resource to respective ones of the FIFO buffers in a buffer order which is based on the priority level of each FIFO buffer. The circuit passes the bits from the FIFO buffers to the respective data communication interfaces and selectively increases the priority level of each FIFO buffer to a second, higher priority level as a function of a level the bits within the FIFO buffer and whether the end of at least one data frame is stored in the FIFO buffer.

Abstract: A DMA controller operable within a host adapter which automatically transmits replies to an attached host system to thereby reduce overhead processing in the I/O processor of the host adapter. The DMA controller is preferably operable to perform DMA transfers in accordance with one or more scatter/gather lists descriptive of the desired data transfer. A flag bit associated with and/or contained in entries of the scatter/gather list signifies the need to transmit a reply message to the host system. The requisite reply message is transmitted to the host system by the DMA controller following the DMA transfer of the block defined by the scatter/gather list entry containing the indicator. The reply message content is determined in accordance with information associated with and/or contained in the subsequent entry of the scatter/gather list. The subsequent scatter/gather list entry includes a reference to the reply message content and a reference to the destination location to which the reply is transmitted.

Abstract: A die including a corrosion monitoring feature is described. The die includes: (i) a surface including an active die region and a scribeline region that is adjacent the active die region; (ii) an insulating layer disposed above the surface and includes a first corrosion sensitive metal plug and a second corrosion sensitive metal plug in the scribeline region; and (iii) a metallization layer positioned above the insulating layer, the first corrosion sensitive metal plug and the second corrosion sensitive metal plug in the scribeline region and the metallization layer disposed above second corrosion sensitive metal plug is patterned to provide the metallization layer with a first opening extending from a top surface of the metallization layer down to a top surface of the second corrosion sensitive metal plug such that a solvent introduced above the top surface of the metallization layer flows into the second corrosion sensitive metal plug disposed below through the first opening in the metallization layer.

Abstract: A method and apparatus for equalizing the frequency response of a transmission line is provided. The method includes the steps of modelling the frequency response of the transmission media for a predetermined frequency range to a predetermined accuracy; determining a desired equalizer response by taking an inverse of the modelled frequency response of the first step; implementing an equalizer that exhibits the desired response; and utilizing the equalizer to equalize the frequency response of the transmission line. The apparatus includes an adaptive equalizer circuit which includes a plurality of signal processor circuits which each take an input signal from the transmission line and process it to mimic a term in a transfer function which represents an inverse of the transfer function of the transmission line. The signals from these processors are then summed and multiplied by a programmable gain term. Then the input is added to the output of the multiplier to form an output equalizer signal.

Abstract: A paged addressing method and associated apparatus for dynamically addressed disk storage subsystem. The present invention stores the logical to physical address map in the disk array. The logical to physical address map is divided into useful sized portions. The logical to physical address map portions containing the most recently used logical to physical address information are retained in cache. Paging techniques are used to swap the logical to physical address map portions from disk to cache when a host disk access requires a logical address not currently within the mapping information in local memory (e.g., cache). The present invention keeps track of the most recently used logical to physical address map portions in cache by defining a cache map. Furthermore, a directory resides in cache that keeps track of the physical address for each logical to physical address map portion. The present invention reduces memory requirements, because the memory map of the disk array is not stored within cache.

Abstract: According to the current invention, there is provided a system for transferring data into and out of a first-in, first-out (FIFO) data buffer. The buffer has a read pointer and a write pointer. The system comprises a comparator circuit, multiple counter blocks, and multiple flag registers. The counter blocks and flag registers are connected to a system clock to provide timing information and capacity indications to the comparator. The comparator circuit continuously monitors the multiple counter blocks, thereby tracking buffer pointer positions. The flag registers indicate relative buffer capacity and provide early indication to the system that the buffer is almost full or almost empty in appropriate conditions. The comparator circuit continuously evaluates the read and write counter blocks and the flag registers to determine the ability of the buffer to accept or transmit data.

Abstract: A computer-based test method and apparatus for measuring DC current drawn by an integrated circuit. The apparatus has a plurality of current measurement ranges and is first initialized to a selected one of the measurement ranges. Next, the apparatus measures the DC current drawn by the integrated circuit in the selected measurement range and increments the selected measurement range if the measured DC current is out of the selected measurement range. The apparatus repeats the steps of measuring and incrementing until the measured DC current is in the selected measurement range. The measured DC current is then compared to a specification limit for the integrated circuit.

Abstract: A high order surface patch rendering system with adaptive tessellation. A patch is rendered by subdividing a patch until the subpatches are sufficiently flat that they can be approximated by a quadrilateral. To subdivide a patch, the patch rendering system uses a patch division unit which accepts the control points of a patch and divides the patch in half by determining the control points of a subpatch. The relationship of the patch to it's subpatches is that of a binary tree, where every patch division produces two subpatches which may themselves be subject to patch division. In one embodiment, the patch division unit is able to traverse the binary subdivision tree in three directions (parent to left-child, left-child to right-sibling, and right-sibling to parent) to minimize memory requirements. In this embodiment the patch division unit comprises a set of curve division units.

Abstract: A system and method for decoding fixed length data words comprising variable length objects is disclosed having the ability to decode a variable length DCT in every clock cycle. The system includes multiple floating point registers, preferably two, for holding the fixed length data words, and a tracking arrangement, including a summation block and a total used bits register, where the summation block sums bits used for each variable length object with the contents of the total bits used register to form the total number of used bits. The total used bits are fed back and summed within the total used bits register.The system also has a rotating shift register, which is a circular buffer, and a multiplexer arrangement which transfers variable length objects from the floating point registers to the rotating shift register. The tracking arrangement counts the bits used in transferring variable length objects to the rotating shift register.

Abstract: The purpose of the present invention is to provide a method for choosing the coding schemes, mappings, and puncturing rates for a modulation/demodulation system which would allow the system to compensate for certain transformations of the code in a post-Viterbi step as opposed to pre-Viterbi. This would allow for faster and simpler decoding of a code.

Abstract: The present invention provides a method for manufacturing a semiconductor device on a substrate. The process involves denuding the substrate by heating to create a denuded zone within the substrate. A screen oxide layer is formed prior to implanting ions into the substrate. This oxide layer remains during the implantation step. The screen oxide layer is removed when forming gates for the semiconductor device.

Abstract: Provided is a universal decoder test board (UDTB) capable of performing the package interface and pin scrambling functions of a conventional DUT board with a variety of different package designs. The UDTB is designed such that it is capable of interfacing with a variety of different tester interface boards, each tester interface board associated with its own hardware manufacturer tester. The UDTB significantly reduces the time and expense invested in test boards required for testing semiconductor device packages for a variety of different manufacturers'platforms by allowing a given package type to be tested with a plurality of testers on the same UDTB.

Abstract: A device for electrically isolating an external device or internal device from an internal signal bus on a semiconductor substrate is disclosed. The device includes a set of drivers which couple an internal signal bus to an external signal bus and a set of drivers which couple the internal signal bus to an internal device signal bus. A driver enable signal generator generates a signal which enables one set of drivers to electrically couple the internal signal bus to either the external device signal bus or the internal device signal bus. The driver enable signal generator generates the driver enable signal in correspondence with the state of a signal indicating the presence or absence of an external device and a signal indicating whether a data transfer operation is occurring. If the external device is present and a data transfer operation is occurring, the internal signal bus is coupled to the external device signal bus.

Abstract: An audio decoder makes use of various component sharing techniques and operates to efficiently prevent deadlock without introducing decoding errors or adding significant complexity to the audio decoder. In one embodiment, the audio decoder comprises a bitstreamer, a synchronization controller, a decode controller, a memory module, a data path, and an output buffer. The bitstreamer retrieves compressed data and provides token-aligned data to the synchronization controller and decode controller. The synchronization controller initially controls the bitstreamer to locate and parse audio frame headers. After each frame header is parsed, the decode controller controls the bitstreamer to parse the variable length code compressed transform coefficients. The coefficients are passed to the memory module and data path which operate under the control of the decode controller to inverse transform the coefficients and produce digital output audio data.

Abstract: A method for automated placement of markers or probe points adjacent to critical timing paths in an integrated circuit design. The markers aid in identifying critical path interconnect lines for purposes of failure analysis or design verification. In a method according to the invention, timing information related to various signal paths in an integrated path is analyzed to isolated critical timing paths. Once a signal path is determined to be a critical timing path, layout data for the critical path is extracted from a layout database. An unused area(s) is then located adjacent to the critical path. Marker information is next inserted into the unused area(s) of the layout database. The act of inserting marker information is performed by a specialized software tool capable of modifying a layout database. Alternatively, existing automated floorplanning or layout tools, or other electronic design automation (EDA) tools, whether proprietary or industry standard, are modified to insert the marker information.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.