Abstract: Methods of planarizing one or more layers having an irregular top surface topology in a semiconductor device based on an underlying MOS structure are disclosed. Methods of creating doped wells or regions for the underlying MOS structure are also disclosed, using thick oxide growths on the surface of the substrate to mask implantation of ions into the wells. A technique for creating a pair of adjacent complementary oppositely-doped wells, such as for a CMOS structure, using a thick oxide growths as a mask is also disclosed. One of the methods of planarizing the one or more layers involves depositing, densifying and re-flowing a layer of glass on top of the topological layer. Another method of planarizing the one or more layers involves depositing, densifying and chemical-mechanically polishing the deposited and densified glass, thereby avoiding an additional temperature cycle (i.e., for re-flowing the glass) which would adversely affect underlying diffusions.

Abstract: A system for optimally locating cells on the surface of an integrated circuit chip is presented herein. The system comprises constructing a plurality of neighborhoods containing elements positionally related to one another; initially evaluating the lowest level of region hierarchy; iteratively developing a logical one-dimensional preplacement of elements on said surface; performing an affinity driven discrete preplacement optimization; evaluating whether a highest level of regional hierarchy has been attained; iteratively performing a dispersion driven spring system to levelize cell density and an unconstrained sinusoidal optimization; executing a density levelizing procedure; iteratively optimizing while controlling element densities; removing element overlap; iteratively optimizing for desired spacing between elements, adjusting element spacing, and permuting elements; locating elements on grid lines; and iteratively performing a functional sieve crystallization.

Abstract: An interconnect bump is formed on a substrate structure of a flip-chip microelectronic integrated circuit by sputtering a metal base layer on the substrate, and then forming a copper standoff on the base layer. A solder cap is formed on the standoff having a peripheral portion that extends laterally external of the standoff. The peripheral portion of the cap is used as a self-aligned mask for a photolithographic step that results in removing the metal base layer except under the standoff and the cap. The cap has a lower melting point than the standoff. Heat is applied that is sufficient to cause the cap to melt over and coat the standoff and insufficient to cause the standoff to melt. The peripheral portions of the cap and the base layer that extend laterally external of the standoff cause the melted solder to form into a generally hourglass shape over the standoff due to surface tension.

Abstract: A remote connection digital processing device with network capability includes on a single chip asynchronous transfer mode (ATM) network protocol processing system interconnection circuits and Motion Picture Experts Group (MPEG) decoder circuits. The ATM interconnection circuits include a physical-layer medium dependent (PMD) unit connected to an ATM network. A transmission convergence (TC)/Framer unit is connected to the PMD unit. An ATM segmentation and reassembly (SAR) unit is connected to the PMD unit. Packet conversion logic is coupled to the ATM SAR unit for converting ATM packets to MPEG format. The MPEG decompression decoder circuits include a demodulator decryption unit coupled to the packet conversion logic. A video decoder is coupled to the demodulator decryption unit. An audio decoder is coupled to the demodulator decryption circuit. A display is coupled to the video decoder. Audio output devices are coupled to the audio decoder.

Abstract: A process for manufacturing a modular multi-pin package for an integrated circuit die is formed of standardized parts and a redesigned, integrated circuit specific circuit substrate possessing a design pattern for providing electrical connection between die pads and output pins. The substrate includes a pattern of electrically conductive traces each terminating in a die pattern at an interior portion of the substrate and terminating in a pattern of pin connecting pads at a peripheral portion of the substrate. A pin holding frame is formed with a plurality of holes in which are inserted a selected number and pattern of package terminal pins, each having a shank protruding outwardly from the pin holder for connection to external circuits or components and each having an inner head pressed against one of the pin connecting pads of the substrate circuit traces.

Abstract: A multi-sided, integrated circuit die includes a plurality of read only memory (ROM) circuits, positioned only at the corners of the die, to simplify qualification testing of new package designs. During qualification testing, electrical and environmental stresses are applied to the package and die combination. The package and die are electronically evaluated at predetermined intervals to determine whether a failure has occurred during testing. When a failure occurs during testing, the package and die are diagnosed to isolate and determine the cause or source of the failure. Package design parameters are adjusted accordingly to reduce or eliminate the occurrence of the failures. An optional 12-bit counter is fabricated onto the die for each ROM circuit to exercise the ROM during qualification testing. An optional process monitor is also fabricated onto the die for each ROM circuit to determine the strength of the fabrication process and the resulting quality of circuit elements produced therefrom.

Abstract: The present invention concerns a method for eliminating or reducing clock skew introduced by differing signal propagation delays across a data bus. At high bus clock frequencies the time delay differences caused by path length differences can be catastrophic and must be eliminated by expensive layout techniques. An input/output (I/O) architecture is proposed here which tailors a delay to each individual data line, and thereby aligns all the incoming data. Furthermore, a clock signal is provided to indicate the optimal data sampling time. In the described embodiment, this circuit enables the transmission of four 32 bit words in parallel in one clock cycle of a 250 MHz processor.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: Disclosed is a method and apparatus for designing re-useable interfacing logic hardware shells which provide interface functions between a hardware core and one or more busses. An interface logic hardware shell provides previously characterized, tested and implemented interface logic designs for use in future applications with little or no redesign. The hardware circuitry (cells) of which such shells are comprised includes circuitry for bus interface units, memory interface units, buffers, and bus protocol logic. The cores for which the shells provide interface functions include CPU cores, memory cores, digital video decoding cores, digital audio decoding cores, ATM cores, Ethernet cores, JPEG cores and other data processing cores.

Abstract: A system for defining a cut point dividing a plurality of cells located on the surface of a semiconductor chip is disclosed herein. The surface has at least one region located thereon. The system comprises dividing each region into subregions, computing the capacity of each subregion, finding the maximum and minimum cell locations within each region, dividing the range spanning the maximum and minimum cell locations into a plurality of subintervals, calculating an index for each cell based on the subinterval containing the cell, accumulating cell heights for each subinterval, determining the values of cell heights for each region as the sum of cell heights for all prior regions, locating the minimum index such that the cell heights for each region are most closely proportional to the capacity of the associated subregion, and finding the cut line based on said minimum index and the maximum and minimum cell locations.

Abstract: Apparatus for use in cooling an integrated circuit structure. The apparatus includes a heat sink having a first portion configured for thermal engagement with an integrated circuit device and a second portion configured for the dissipation of heat into an ambient fluid, such as air. The heat sink is made from a powdered metal which, in one preferred embodiment, includes copper. The heat sink may be formed from the plurality of discrete layers, each layer having a button projecting from one surface, and a depression formed in an opposing surface. The depression is configured to receive a projecting button portion from another layer. In an alternative embodiment the heat sink includes a plurality of plugs projecting from the generally flat surface.

Abstract: An integrated circuit package includes a heatspreader which is formed to have a centrally disposed recessed portion between planar surfaces, and flex tape extending from the planar surfaces into the centrally disposed surface. A semiconductor chip is mounted on the centrally disposed surface between the flex tape, and wire bonds interconnect bonding pads on the chip to the metal interconnect patterns on the flex tape. Plastic molding or epoxy is then applied to encapsulate the chip and wire bonding in the centrally disposed planar surface of the heat spreader. The package is then readily mounted on a motherboard using solder balls.

Abstract: The subject invention is directed to a method for producing semiconductor wafers using a simplified hole interconnect process. These wafers include at least one interconnect layer located on a contact or via layer. As contrasted with the semiconductor wafers produced according to the prior art method described above, the contact or via layer of this invention includes a plurality of patterned openings formed therein which are in substantial alignment without offset with each other.

Abstract: An MPEG decoder system and method for performing video decoding or decompression which includes a unified memory for multiple functions according to the present invention. The video decoding system includes transport logic, a system controller, and MPEG decoder logic. The video decoding system of the present invention includes a single unified memory which stores code and data for the transport, system controller and MPEG decoder functions. The single unified memory is preferably a 16 Mbit memory. The MPEG decoder logic includes a memory controller which couples to the single unified memory, and each of the transport logic, system controller and MPEG decoder logic access the single unified memory through the memory controller. The video decoding system implements various frame memory saving schemes, such as compression or dynamic allocation, to more efficiently use the memory.

Abstract: Microelectronic devices are formed on a substrate of an integrated circuit. An electrically conductive ground or power plane, and an ElectroStatic Discharge (ESD) protection layer are formed on the substrate. Terminals such as solder ball or wire bond pads are formed on the substrate, and are electrically connected to the devices. The protection layer is patterned such that portions thereof are disposed between the terminals and the plane to define vertical electrical discharge paths. The protection layer is formed of a material such as SurgX.TM. which is normally dielectric, and is rendered conductive in the discharge paths by an electrostatic potential applied to the terminals during an ESD event to shunt the electrostatic potential from the terminals to the plane. Alternatively, the protection layer can be formed between the terminals to define lateral discharge paths.

Abstract: A system for optimizing the density of cells located on a surface of a semiconductor chip divided into a plurality of rectangular regions is provided herein. The corners of these regions define nodes. The system comprises computing an average local cell density for regions adjacent to each node and deforming these regions by relocating nodes to positions that minimize a cost function associated with the densities of the new deformed regions bordering the relocated nodes.

Abstract: The present invention provides a method and apparatus for conditioning a polishing pad in which slurry is directed under pressure at the polishing pad. Additionally, energy (i.e., ultrasonic energy) may be added to the slurry as it is directed towards the polishing pad, wherein embedded material in the polishing pad is removed or dislodged.

Abstract: One or more non-overlapping moving windows are positioned over a placement of cells for an integrated circuit chip to delineate respective subsets of cells. A fitness improvement operation such as simulated evolution is performed on the subsets simultaneously using parallel processors. The windows are either moved to specifically identified high interconnect congestion areas of the placement, or are moved across the placement in a raster type pattern such that each area of the placement is processed at least once. Exchange of misplaced cells between subsets can be accomplished by dimensioning the windows and designing the window movement pattern such that the subsets overlap. Alternatively, such exchange can be accomplished by using two sets of windows of different sizes. As yet another alternative, the improvement operation can allow misplaced cells to move to a border area outside a window.

Abstract: A DBS receiver front end which includes a tuner chip and a demodulator/decoder chip having digital interface signals. The tuner chip is configured to receive the digital signals at a reduced peak-to-peak amplitude to reduce the digital interference noise in the tuner chip. The digital signals may also have a limited slew rate to further reduce the digital interference noise. The tuner chip is configured to convert a receive signal to a baseband signal, and the demodulator/decoder chip is configured to convert the baseband signal to a decoded signal.

Abstract: A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure.