Abstract: A system for computing an affinity for relocating a cell from a location on a surface of a semiconductor chip is disclosed herein. Each cell may be associated with a net connecting a plurality of cells. The system first partitions the surface into a number of regions and computes capacities of lines dividing the regions and number of nets crossing the lines. The system then calculates penalties based on the number of net crossings and the capacities of lines and determines the total affinity based on relative improvements for lines crossed by the nets.

Abstract: A video decoder system for reconstructing, storing and retrieving bidirectionally predictive-coded (B) frames for display including pull-down conversion includes a reconstruction unit for reconstructing the frames, where the reconstruction unit reconstructs the top-upper field of every other frame twice. The frame is conceptually divided into four sections, including top-upper, top-lower, bottom-upper and bottom-lower sections. A memory having only three segments for storing pixel data is provided, where each segment is sized to store any one of the frame sections. A segmentor receives and separates the pixel data according to the top and bottom fields for each section of each frame, and stores pixel data from the top field into one segment pixel data from the bottom field into another segment. The segrnentor initially selects any two segments for the upper half of the first frame, and then selects a segment being retrieved for display and the third segment for the bottom half of the first frame.

Abstract: A method for determining the thickness of a film in a film stack using reflectance spectroscopy is provided in which one of the films in the stack has unknown optical constants. Conventional methods of using reflectance measurements to determine the thickness of a film require knowledge of the thicknesses and optical constants of all underlying films. An embodiment involves forming a test layer across a substrate having a known thickness and known optical constants. The thickness of the layer is determined using reflectance measurements. A first layer of the same material is then formed across a second layer at the same conditions that the test layer was formed. Thus, the test layer and the first layer can be assumed to have the same thicknesses. A spectral response curve may be determined for the first layer. The first layer is then processed so that its thickness is no longer known.

Abstract: A tape ball grid array (TBGA) package, and a method of making a TBGA package, includes the use of a metal or other stiffener affixed to a flexible tape on which conductive traces connect contact points on an integrated circuit (IC) chip with an array of solder balls. The stiffener is perforated with a pattern of small vent holes. The TBGA package materials are hygroscopic. When the TBGA package is heated during 2nd level packaging, e.g., during solder reflow, moisture absorbed within the hygroscopic materials evaporates and the resulting water vapor is able to escape through the vent holes, rather than becoming trapped within the IC package and introducing various 2nd level packing failure modes.

Abstract: A concatenated three layer Viterbi, Reed-Solomon/Deinterleaver and Descrambler forward error correction decoder may be utilized in digital video and audio systems, and for direct broadcast satellite applications. The digital signal may be a compressed video and audio signal transmitted from a direct broadcast satellite. Acquisition for three layers of synchronization are required, but once all three layers are in-sync, down stream data synchronization monitoring will suffice so that upstream synchronization monitoring can be disabled thus improving system robustness to noise bursts and false synchronization on false sync bytes generated at the transmission encoder during non-changing data signal conditions.

Abstract: A semiconductor package for preserving clearance between encapsulant and a printed circuit board is provided including a package substrate having an upper surface and a lower surface, wherein the upper surface is attached to a heat spreader and the lower surface is electrically coupled to a printed circuit board by a plurality of high temperature solder balls, the solder balls being formed from a metal such as lead, tin or copper; a semiconductor die, the non-active side of which is coupled to the heat spreader, and which is electrically coupled to the substrate by bond wires joining bond pads on the active side of the semiconductor die to electrical traces formed on the package substrate; an encapsulant covering the semiconductor die and the bond wires such that the encapsulant forms a protrusion from the lower surface of the package substrate; and a lid having a plurality of stand-off legs, each leg being formed at a corner of the lid, disposed over the encapsulant which establishes the height of the protru

Abstract: Described is an portion of an integrated circuit structure formed on a semiconductor substrate which provides electrostatic discharge (ESD) protection, utilizing an SCR structure, and also inhibits latchup of the SCR structure. The integrated circuit structure comprises an ESD protection device and an adjoining driver section matched together so that the width dimension of the ESD protection device matches the sum of the length of the adjacent driver section plus twice the width of a doped portion of the substrate forming a guard ring surrounding the driver section. When the length dimension of the MOS structure of the driver section is so maximized by further repeating of the source/gate/drain regions, the physical width dimension of the MOS structure of the driver section may be reduced without reducing the effective width of the MOS structure of the driver section, i.e., the effective width of the MOS structure remains sufficient to permit the required amount of power to be handled by the driver section.

Abstract: A semiconductor die is disposed on a side of an optically-transmissive preformed planar structure (interposer), and an optical element is disposed on an opposite side of the interposer. The interposer may be provided with through holes extending at least partially into the die side, and electrical probes in the through holes, for making contact to raised conductive bumps on the die. The interposer may be provided with raised portions for locating the optical element at a predetermined distance away from the die. The interposer may be provided with darkened areas for preventing light from impacting selected areas of the die.

Abstract: A simulation based power analysis tool extracts "expected" current waveforms from simulation results. These expected waveforms are then used to represent the power consumption for a corresponding circuit cell or groups of cells from which the waveform is derived. The expected waveform is a statistical representation of a current derived over a number of cycles. The expected waveform is derived by recording the starting time of each power arc with respect to a tool defined clock period. The width of the waveform is derived from the average current, propagation delay and intrinsic delay for arc. The expected waveform can take several forms depending on the accuracy required. Each form has a corresponding memory storage requirement. The starting time for each arc can be stored, which yields the most accurate "true" expected waveform. Alternatively, the minimum, maximum and average starting times for a given power arc can be stored from which a "weighted min-max" expected waveform can be constructed.

Abstract: A test circuit is provided for detection of data retention faults and cell stability faults of a memory array, such as a static random access memory (SRAM). The memory array test circuit comprises a weak write test circuit, a memory array address decoder, a microprocessor and display unit. During testing of the memory array, the weak test circuit controls the address decoder to decrease the voltage on the word lines so that it is less than the threshold voltage of the memory array transistors. The microprocessor then writes an inverted data to the memory array and then reads it. The read inverted data is sent to the display unit for comparison with a known template. By comparing the read inverted data to the template, defective memory cells can be identified.

Abstract: A method is provided for operating a scan chain in a semiconductor device having a plurality of serially connected logic blocks, an output from a first logic block being coupled to an input of a first latch, the output from the first latch being coupled to the input of a second logic block, an output of the second logic block being coupled to an input of a second latch, the method comprising: detecting a test enable signal; if the test enable signal is active: detecting the output of the first latch, and setting the output of the second latch to the same state as the detected output of the first latch, independently of the state of the output of the second logic block; if the test enable signal is inactive: setting the output of the second latch responsive to the output of the second logic block.

Abstract: An integrated circuit device package of this invention includes a flexible substrate having an upper patterned insulative layer, and a lower patterned conductive layer including a plurality of package leads. An integrated circuit die is fixed within a void of the upper surface of the flexible substrate. Electrical connections between the integrated circuit die and the package leads are provided. A rigid upper protective layer is present. The rigid upper protective layer encloses the integrated circuit die, and at least partially covers the top surface of the upper insulative layer. The semiconductor device package further comprises a rigid or semi-rigid metal lower protective layer opposite the upper protective layer including a ground plane proximal to the electrical leads and a power plane distal to the leads. Methods of production are also given.

Abstract: A high speed Advanced Programmable Interrupt Controller (APIC) system includes a plurality of local units for prioritizing and passing interrupts, an Input/Output (I/O) unit for feeding interrupts to the local units, and a serial link data transmission system for interconnecting the I/O unit and the local units. The I/O unit and each local unit have a parallel I/O interface.

Abstract: A shared memory fabric architecture for asynchronous transfer mode (ATM) switches including a multi-dimensional array of electrically interconnected N*M switch modules, where N>>M. The fabric architecture also includes input ports for providing cells to the array of switch modules. The input ports operate at a predetermined speed S. The fabric architecture additionally includes memory devices electrically connected to the array to provide a hierarchical memory structure at each switch module. The memory devices include on-chip, high-speed memory devices operating at a high-speed memory speed of N*S and off-chip, low-speed memory devices operating at a low-speed memory speed of (Y+M)*S, where Y<<N.

Abstract: A system for determining an affinity associated with relocating a cell located on a surface of a semiconductor chip to a different location on the surface is disclosed herein. Each cell may be part of a cell net containing multiple cells. The system initially defines a bounding box containing all cells in the net which contains the cell. The system then establishes a penalty vector based on the bounding box and borders of a region containing the cell, computes a normalized sum of penalties for all nets having the cell as a member, and calculates the affinity based on the normalized sum of penalties.

Abstract: A method for producing a relatively thin titanium nitride barrier layer in an integrated circuit is presented. The titanium nitride layer may be utilized in a tungsten plug interconnection by providing a semiconductor wafer with a conducting layer covered by an insulating layer. The insulating layer is patterned and etched to form contact holes or vias. A layer of titanium is deposited on the surface of the wafer including the sidewalls and bottom of the via. A relatively thin titanium nitride layer is then formed on the titanium layer. The formation of the titanium nitride layer includes growing titanium nitride by a reaction of a nitrogen-bearing species with the titanium layer. The titanium nitride layer prevents the underlying titanium layer from reacting with the subsequent tungsten layer which is deposited on the wafer to fill the via. The tungsten layer is then etched so that the tungsten remaining forms a plug interconnection between conducting layers.

Abstract: A method derives edge extensions for wavelet transforms and inverse wavelet transforms of two-dimensional images. The method overcomes the necessity of side computations by treating the two-dimensional matrix of values as a one-dimensional array of values. The use of a one-dimensional array reduces the required flushing and loading of registers by allowing the flushing and loading to be performed in between frames, rather than in between rows or columns of the matrix.

Abstract: Various forms of micromachined electrostatic microconveyors and useful devices based thereon are described. In one embodiment, a tube shaped conveyor is formed by disposing conductors circumferentially about the exterior surface of the tube. The tube is formed of an insulating material (e.g., silicon dioxide). Driving voltages are applied in staggered phase to selected ones of the conductors to provide a travelling electrostatic wave within the tube. Charged particles (or fluid or gas) can be propelled through the tube electrostatically by "riding" the travelling wave. Various aspects of the invention are directed to apparatus making use of the microconveyor to convey particles, gas ions, etc. Apparatus is described for using gas pressure resulting from the transport of gas ions to do mechanical work (i.e., to operate mechanical actuators.

Abstract: A single ended bit line sensor includes a single ended bit line input, a sensor output, an inverting amplifier, a non-inverting amplifier and a differential amplifier. The inverting amplifier is coupled to the single ended bit line input and has a first voltage output. The noninverting amplifier is coupled to the single ended bit line input and has a second voltage output. The differential amplifier has first and second amplifier inputs coupled to the first and second voltage outputs, respectively, and has an amplifier output coupled to the sensor output.

Abstract: The present invention provides a local rip-up and reroute (LRR) method to reduce the number of open nets after the initial routers have been applied. Two main tasks are performed under this method. The first task is to identify a locally blocked pin and rip up wire segments in an area around the cell having the locally blocked pin. The second task is to reroute the now freed locally blocked pin. In the first task, an open net is read from the list of open nets. The pins of this open net are identified and determined if they are locally blocked. A pin is considered as locally blocked if a routing path, starting from the pin, cannot be found within N grid point expansions. If a pin is locally blocked, segments of wires within or at the boundary of a predefined bounding box are removed (or ripped-up)--except for two situations. The first exception is that a wire that is connected to a pin is not ripped-up.