Abstract: A DRAM array embedded in an IC, ASIC or a SLIC includes a plurality of redundant functional elements and a substitution circuit which responds to signals communicated from a bus to electrically connect selected ones of the redundant elements as fully functional replacements for corresponding defective elements of the DRAM array. The redundant elements include bit blocks and word line groups. The substitution circuit includes a controllable selector which electrically connects selected ones of the bit blocks and word lines to respond to data and address signals communicated on the bus. A register responds to bus control signals and supplies signals to achieve connection of the redundant elements. The defective elements are identified, and the replacement redundant elements are substituted, by testing the elements of the DRAM array for proper functionality and processing the results of the test.

Abstract: On integrated circuit designs employing large, pre-defined circuit blocks, chip area utilization and signal routing is improved by permitting signals between circuit blocks surrounding (e.g., on opposite sides of) a large circuit block (megacell) to physically pass through the megacell. The megacell is laid out so that a "parting line" is defined through the megacell. Circuits within the megacell are laid out so that no circuit "straddles" the parting line. The megacell can then be split or stretched about the parting line to create a wiring channel. The wiring channel is used for routing signals from the surrounding cells (circuit blocks) through the large circuit block (megacell). Signals between the separated portions of the stretched or split megacell on opposite sides of the parting line may be routed in one metal layer, while connections of surrounding cells through the megacell may be routed in another metal layer.

Abstract: A process is disclosed for forming one or more doped regions beneath the surface of a single crystal semiconductor substrate, such as retrograde wells or deeper source/drain regions, by implantation at low energy which comprises orienting the crystal lattice of the semiconductor substrate, with respect to the axis of the implantation beam, i.e., the path of the energized atoms in the implantation beam, to maximize the number of implanted atoms which pass between the atoms in the crystal lattice. This results in the peak concentration of implanted atoms in the crystal lattice of the single crystal semiconductor substrate being deeper than the peak concentration of implanted atoms in the substrate would be if the axis of the implantation beam were not so oriented with respect to the crystal lattice of the semiconductor substrate during implantation.

Abstract: In a multifunction PCI device containing identical backend functions or other large, redundant functional blocks, a single backend function is selected as a primary function while in test mode. All backend I/O channels are then simultaneously tested in parallel, with the same data and control signals from a PCI local bus being driven to all backend channels during the same test clock cycle. A single backend channel is designated as the primary for providing requisite handshaking signals during output to the backend I/O channels. Input data from each backend channel is received in parallel and compared, with miscompares being flagged to allow testing of the input data path from the respective backend I/O channel. Only signals from the primary backend I/O channel are designated for transmission to the PCI local bus. Signals from the remaining backend channels are received in parallel with and compared to the signals from the primary channel, and miscompare flags are generated for any discrepancies identified.

Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates.

Abstract: A Motion Picture Experts Group (MPEG) video/audio data bitstream comprises frames of encoded audio data, each of which includes a plurality of integrally encoded subframes, which are decoded by an audio decoder for presentation. A synchronization unit controls the decoder to skip a subframe if a predetermined decoding time for the subframe is earlier than a current time, and to repeat the subframe if the predetermined decoding time is later than the current time. A typical MPEG audio frame includes 12 subframes, such that skipping or repeating a subframe is 1/12 as noticeable as skipping or repeating an entire frame. A buffer memory stores one or more subframes prior to decoding, such that the subframes can be skipped or repeated by manipulation of a read pointer for the memory.

Abstract: Disclosed is a failure analysis tool including a production tester electrically coupled to a test IC in such a manner that it can test the IC in a conventional manner (e.g. by providing a series of dynamic vectors), and also provide an OBIC signal to an OBIC detection system. This is accomplished by providing power to the IC through a voltage source having a non-zero internal resistance while the OBIC signal is generated, thus preventing the OBIC signal from shorting to ground when it is received at the power supply. Failure analysis is conducted by first performing functional testing with a production tester until a failing state is identified. While this functional testing is being performed, the internal resistance of the voltage source is set to zero. Then, when the failing state is identified, the internal resistance of the voltage source is set to a non-zero value and the IC is scanned by an optical beam to generate OBIC signals indicating the locus of the failure.

Abstract: The formation of a cobalt silicide layer of uniform thickness over the source/drain regions and the polysilicon gate electrode of an MOS structure, which does not thin out adjacent the edges of the top surface of the polysilicon gate electrode, i.e., adjacent the oxide spacers, is achieved by first forming a titanium capping layer over a cobalt layer deposited over the MOS structure prior to formation of the cobalt silicide, and while excluding oxygen-bearing gases from the cobalt surface prior to the deposition of the titanium capping layer.

Abstract: Systems and methods of verifying the design of the ASIC during design and implementation phases are provided. The ASIC design is verified utilizing information from a system simulation in the customer's system environment. During system simulation, the invention captures "golden" vectors that may be used to test the ASIC during stand-alone simulation. The outputs generated by the ASIC during stand-alone simulation are compared to the outputs generated during the system simulation. Thus, the customer's system simulation is reproduced without having to reproduce the customer's system environment which allows the operation of the ASIC to be verified during various states of synthesis. Additionally, the test bench for testing the ASIC in stand-alone simulation is automatically generated eliminating the need for the user to manually generate a test bench.

Abstract: A method for testing refresh operations of a memory array wherein subthreshold leakage current may be set to near worst-case conditions. The memory array includes a first row of memory cells having a first memory cell configured to store a first memory value, and a second row of memory cells having a second memory cell configured to store a second memory value. The method comprises storing a logic high value to the first memory cell as the first memory value, followed by storing a logic low value to the second memory cell as the second memory value. The method further comprises repeatedly driving a write bit line coupled to both the first and second memory cells at a logic low level for a period of a time equal to a refresh interval corresponding to the first memory cell. Additionally, the method includes subsequently reading the first memory value from the first memory cell.

Abstract: A process for forming a photoresist mask over a patternable layer of an integrated circuit structure formed on a semiconductor substrate is described wherein the photoresist mask is initially formed with oversized lateral dimensions over a layer of patternable material of an integrated circuit on a semiconductor substrate. The oversized resist mask is then optionally measured in a vacuum apparatus to determine the size of the critical dimensions; then dry etched, preferably in the same vacuum apparatus, to reduce the size of the resist mask; then measured to determine the size of the critical dimensions (preferably again in the same vacuum apparatus); and then, if necessary, further dry etched to further reduce the size of the critical dimensions. The dry etching and subsequent measurement steps are repeated until the desired critical dimensions of the resist mask are reached.

Abstract: A method in a data processing system for identifying hazards in a circuit. Signal paths are identified in the circuit. Each signal path within the plurality of signal paths begins at a source and ends at a target and each signal path within the signal paths is one that potentially propagates a hazard. Errors are then identified in signal paths in the circuit by analyzing the timing relationships and hazard characteristics of the signals within the signal paths.

Abstract: A video decoder which uses a dynamic memory allocation scheme having additional buffer read pointers for implementing a freeze mode. The additional buffer read pointers advantageously allow for implementation of a freeze mode on a dynamic memory allocation architecture. In one embodiment, the video decoder includes an MPEG bitstream decoder, FIFO buffer logic, a free segment register, and a display processor. The video decoder decodes an encoded bitstream to obtain image data for storage in an external memory, and the display processor retrieves the image data for display on a monitor. To conserve memory, the bitstream decoder stores only anchor frames as complete images in the external memory, and bi-directional images are stored in dynamically allocated memory segments. Free memory segments are determined by examination of a free segment register, and pointers to the memory segments having image data are passed to the display processor via the FIFO buffers.

Abstract: A method for mounting an integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit onto to a circuit board. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount.

Abstract: In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement.

Abstract: A reduced netlist representing only partial netlist information for a logic block such as an ASIC embedded core is generated, such that proprietary information contained within the netlist can be kept confidential. The core is conceptually divided into a first section that can be completely tested using only a serial scan port, and a second section that can be tested in isolation from the first section using both primary inputs to the core as well as scan inputs. Netlist information for the first section is removed from the netlist, and the customer is supplied with serial scan test vectors that test the first section. Additionally, a multiplexing circuit selects either a serial scan chain for the entire logic block, or a scan chain that does not include scan cells within the first section of the logic bloc.

Abstract: Disclosed is a pair of conductive rings and method for making the conductive rings for introducing an integral network of capacitive structures around a semiconductor die of a semiconductor package. The pair of conductive rings include a ground rail ring that is defined around a semiconductor die pad that is configured to receive a semiconductor die. The ground rail ring has a first plurality of extension spokes that extend away from the ground rail ring. The pair of conductive rings further includes a power rail ring that is defined around the semiconductor die pad. The power rail ring has a second plurality of extension spokes that extend away from the power rail ring and toward the ground rail ring.

Abstract: Disclosed is a reusable hardware layout ("core") for performing some, but not all, MPEG-2 video decoding functions. The information content of the core may be stored on a machine readable media and includes a series of hardware layouts specifying the locations and features of various circuit elements comprising the video core architecture. The disclosed video decoder core design specifies that at least the following MPEG-2 functions are performed by the hardware: inverse scan, inverse quantization, inverse discrete cosine transform, half pel compensation, and merge. Other MPEG-2 functions such as motion vector decoding, variable length decoding, and run level decoding are not performed by hardware video cores fabricated in accordance with video core design.

Abstract: A method and apparatus for detecting when a second object touches a digitizing panel while a first object is touching the digitizing panel is disclosed.

Abstract: A stackable heat sink assembly is formed by press-fit assembly of two or more identical fin layers. Each fin layer is formed using powdered metallurgy and has a button-like projection extending from its bottom surface and a recess opening in its top surface. The button-like projection and recess opening are sized and shaped such that an interference fit is formed when the button-like projection of one fin layer is pressed into the recess of another fin layer. The use of an adaptor to increase or decrease the effective size of the button-like projection of the bottommost fin layer is described. Relieving gases that may be entrapped in the recess during assembly is described. Circular, elliptical and polygonal shapes (outlines) for the fin layers are described.