Abstract: A voltage comparator circuit includes a comparator 42 having a first comparison input, a second comparison input and first and second switched current memories 52, 58 (e.g., switched FETs) connectable, respectively, to the first and second comparator inputs for input voltage offset compensation. In use, during a storage phase, a current value is stored in the switched current memory for each of the first and second comparison inputs and, during a comparison phase, the stored current values are used to compensate for voltage offsets between the comparison inputs.

Abstract: VLSI I/O structures to reduce the effects of simultaneous switching noise (SSN) on output driver circuits and enhance electrostatic discharge immunity, while reducing chip area, in both input receiver circuits and output driver circuits include improved transistors having deep-junction drain and a multi-cascaded, resistive deep-junction source structure.

Abstract: A DBS receiver front end which converts the received signal directly to the baseband representation and maintains a high performance with a new techniques for tracking and counteracting frequency drift and I/Q angular error. The DBS receiver front end comprises a tuner and a demodulator/decoder. The tuner receives a high frequency signal and converts it to a baseband signal having a frequency offset error. In one embodiment, the DBS receiver front end includes a demodulator/decoder which receives the baseband signal and produces a compensation signal for canceling the frequency offset error. The demodulator/decoder performs the frequency-offset error compensation digitally. The demodulator/decoder includes an A/D converter which over-samples (samples at a rate of more than two samples per symbol period) the baseband signal and converts it to digital form.

Abstract: A reusable hardware layout ("core") for performing some, but not all, MPEG and AC-3 audio decoding functions. Specifically, the audio core performs matrixing and windowing operations of MPEG and AC-3 decoding. The disclosed audio core design includes a data path, a control logic unit, an input RAM interface (for controlling an input RAM), an output RAM interface (for controlling an output RAM), a ROM, a ROM addressing logic unit, and a registers interface. The input RAM and the output RAM are located outside of the audio core. The control logic unit specifies in which state of multiple states the audio core currently resides, with each of the multiple states specifying one function or group of functions of either the MPEG or AC-3 decoding process. The control logic unit includes an MPEG state machine for generating MPEG state and cycle count information and an AC-3 state machine for generating AC-3 state and cycle count information.

Abstract: A method for creating a shell to represent a functional block of an IC design comprising of a plurality of interconnected functional blocks. The critical information from a synthesized gate level block is retained in the shell such that when analyzing the static characteristics of another block connected to the block now represented by the shell the analysis is still accurate. At a hierarchial level the present invention provides a method for analyzing the functional blocks of an IC design such that the memory requirement for storing the information of the functional blocks of the IC design is reduced as well as a decrease in run time.

Abstract: A DIP integrated circuit package is disclosed which includes a trench-type DRAM and an associated non-symmetric lead frame having one or more Y-shaped leads which branch in the direction of die I/O pads. Such non-symmetric lead frames allow multiple use of pin spacing (i.e., one pin may be used to connect to widely spaced I/O pads on the DRAM die). Further, such structures serve to dissipate the generated heat, and thereby reduce noise, in high density trench-type DRAMs, such as 64 Mbit DRAMs. The lead frame is provided as a DIP lead frame which has no die attach pad and is wire bonded to I/O pads of the integrated circuit that are provided along a center line on the chip.

Abstract: A system for improving the position of cells located on a surface of a semiconductor chip having at least one region located thereon is disclosed herein. The system calculates affinities for relocating the cell to an alternate region, computes a first threshold, and repositions all cells having a maximum affinity greater than the first threshold to the region providing the maximum affinity for the cell.

Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.

Abstract: A ball grid array package utilizes solder balls having central cores of a material with a higher melting point than solder material surrounding the core. When the ball grid package and motherboard assembly are heated to the melting point of the solder material, the cores remain solid and function as spacers in preventing direct contact of the package surface and the motherboard surface, thus preventing molten solder from being squashed and flowing to adjacent ball contacts.

Abstract: A memory circuit which uses multiple storage mechanisms in each of its memory cells. In one embodiment, the memory circuit comprises a memory cell array and a data sense module. Each cell of the array includes a first, second and third transistors, and a capacitance. The first transistor has a first gate coupled to a first word line, a floating gate which stores a first charge, a first source coupled to a first data line, and a first drain. The second transistor has a second gate coupled to the first drain, a second source coupled to a second word line, and a second drain. The third transistor has a third gate coupled to a third word line, a third source coupled to the second drain, and a third drain coupled to a second data line. The capacitance is coupled between ground and the third source. The capacitance stores a second charge when the second word line is asserted and the third word line is de-asserted. The second gate stores a third charge when the first word line is de-asserted.

Abstract: A multiprocessing system includes a plurality of data processing subsystems each coupled to an interprocessor communications bus through a corresponding interprocessor communications interface. The interprocessor communications interface corresponding to each data processing subsystem includes a receive FIFO buffer unit, a transmit FIFO buffer unit, and a control circuit. When a data processing subsystem desires to transfer data to another processing subsystem, the data processing subsystem packetizes the data in a variable word-length transfer packet which includes a header having a size field and a target field. The data processing subsystem causes the transfer packet to be stored within the transmit FIFO buffer unit. When a valid transmit packet is stored with the transmit FIFO buffer of the interprocessor communications interface corresponding to a particular processing subsystem, the associated control unit requests mastership of the interprocessor communications bus and transmit packet.

Abstract: A ball grid array package in which one or more conductive rings are positioned on a surface of the package substrate along with solder bond contacts on the surface of the substrate to facilitate the interconnection of wire bonds to an integrated circuit chip on the surface of the substrate. The use of rings allows for better distribution of power to the chip since a plurality of wires can be connected between the chip and the conductive rings for power distribution. The rings create a different shelf for the power and ground bonds on the substrate, and by providing a vertical separation between the surfaces of the rings and bonding pads on the surface of the substrate more bonds in the package can be accommodated.

Abstract: A uniformly doped polysilicon gate electrode of an MOS device forming a part of an integrated circuit structure on a semiconductor substrate is formed by first depositing a very thin layer of amorphous or polycrystalline silicon, e.g., from about 2 nm to about 10 nm, over a gate oxide layer. The thin layer of silicon layer is then exposed to a nitrogen plasma formed from N.sub.2 at a power level sufficient to break the silicon--silicon bonds in the thin layer of silicon, but insufficient to cause sputtering of the silicon to cause a barrier layer of silicon and nitrogen to form at the surface of the thin silicon layer. Further silicon, e.g., polysilicon, is then deposited over the barrier layer to the desired thickness of the polysilicon gate electrode. The gate electrode is then conventionally doped, i.e.

Abstract: Signals (including probes) from an external system are selectively connected to a plurality of unsingulated dies on a semiconductor wafer with a minimum number of connections and an electronic selection mechanism resident on the wafer. The electronic selection mechanism is connected to the individual dies by conductive lines on the wafer. The electronic selection mechanism is capable of providing the external signals (or connecting the external probe) to a single die or groups of the dies, and electronically "walking through" the entire plurality of unsingulated dies. Redundant conductive lines may be provided. Diodes and/or fuses may be provided in conjunction with the conductive lines, to protect against various faults which may occur in the conductive lines. Redundant electronic selection mechanisms may also be provided to ensure the ability to selectively provide signals to the unsingulated dies.

Abstract: A random number generating apparatus for an interface unit of a Carrier Sense with Multiple Access and Collision Detect (CSMA/CD) Ethernet data network. The interface unit includes a transmit backoff unit for implementing a backoff algorithm in response to a network collision signal and a random number. The apparatus comprises a dual mode random number generator and a multiplexer for switching the random number generator between modes in accordance with the serial address bits of a data packet being processed by the interface unit. The random number generator includes a 25 stage linear feedback shift register. The multiplexer has two signal inputs connected to outputs of the 18th and 22nd stages of the shift register respectively, a switch input connected to receive the serial address bits and an output connected in circuit to an input of the shift register.

Abstract: A trench etching process is disclosed in which a substrate is etched under conditions that promote forward sputtering of mask material in a plasma reactor having at least three electrodes. The forward sputtering impedes etching of trench sidewalls by depositing a protective layer of mask material on the sidewalls of a trench being formed. By controlling the amount of forward sputtering, one can control the trench profile and aspect ratio (depth to width). By employing forward sputter etching in a three or more electrode reactor, trenches of less than one micron in width and having aspect ratios of at least 2.5:1 are formed. Such trenches are used in trench capacitors of high density DRAMs. A disclosed plasma reactor includes a grounded first electrode which forms part of the reactor's enclosure, a coiled second electrode disposed above and separated from the reactor enclosure by a dielectric shield, and a planar third electrode located below the substrate to be etched.

Abstract: An initial placement of cells, and a routing including wires interconnecting the cells, is provided for a microelectronic integrated circuit. A grid is defined as including a plurality of first gridlines that extend parallel to a first axis, and a plurality of second gridlines that extend parallel to a second axis that is angularly displaced from the first axis. The cells are represented as vertices located at intersections of first and second gridlines, and the wires are represented as edges that extend along the first and second gridlines. Clusters of vertices are created such that each cluster includes vertices located on a respective first gridline. A "cover" is computed as including a minimum block of clusters that are connected to all other clusters by wires extending along the second gridlines. Clusters outside the cover are spatially reordered along the second axis away from the cover in descending order of numbers of wires extending from the clusters along the second gridlines.

Abstract: A conversion system for converting run-level pairs into variable length codes (VLCs) for purposes of compression, where each run-level pair includes a run and level value derived from scanning blocks of DCT coefficients. Each run value is provided to a programmable memory, which stores a segment address table comprising a list of base addresses, where a base address is included for each valid run value. An adder is provided for adding the base address to the level value of the run-level pair for determining a VLC address. The VLC address is provided to another programmable memory, which stores a table of VLCs, where the VLCs are grouped according to corresponding run values into a plurality of run segments, where each run segment corresponds to one run value and where each group of VLCs are ordered according to level values. The VLCs are preferably organized in ascending order based on the level values.

Abstract: A system for computing an affinity for relocating a cell from a location on a surface of a semiconductor chip is disclosed herein. Each cell may be associated with a net connecting a plurality of cells. The system first partitions the surface into a number of regions and computes capacities of lines dividing the regions and number of nets crossing the lines. The system then calculates penalties based on the number of net crossings and the capacities of lines and determines the total affinity based on relative improvements for lines crossed by the nets.

Abstract: A method for determining the thickness of a film in a film stack using reflectance spectroscopy is provided in which one of the films in the stack has unknown optical constants. Conventional methods of using reflectance measurements to determine the thickness of a film require knowledge of the thicknesses and optical constants of all underlying films. An embodiment involves forming a test layer across a substrate having a known thickness and known optical constants. The thickness of the layer is determined using reflectance measurements. A first layer of the same material is then formed across a second layer at the same conditions that the test layer was formed. Thus, the test layer and the first layer can be assumed to have the same thicknesses. A spectral response curve may be determined for the first layer. The first layer is then processed so that its thickness is no longer known.