Abstract: A reprogrammable address selector is incorporated in an embedded DRAM array which has a plurality of addressable DRAM components. The reprogrammable address selector responds to an address signal defining a unique response address. One of a plurality of selected response addresses may be electrically and selectively programmed into the selector as a substitute for a fixed response address. Thereafter the addressable DRAM component responds to the programmed response address rather than the fixed response address. The programmed response address is programmed from address signals applied on the bus.

Abstract: An output driver for an integrated circuit. The output driver includes a core data terminal, a pad terminal, a pull-down transistor and a pull-up transistor. The pull-down and pull-up transistors are coupled to the pad terminal and have pull-down and pull-up control terminals, respectively. A first inverter circuit coupled between the core data terminal and the pull-down control terminal. First and second voltage level shifting differential amplifiers are coupled in series between the core data terminal and the pull-up control terminal.

Abstract: A fluxless method for fusing preformed solder balls to contact pads on a semiconductor package substrate wherein a masking plate having one or more vertical holes corresponding to the contact pads is placed over the package substrate, oxide-free solder balls are placed in the holes, the assembly is preheated to a temperature less than the melting point of the solder, and an energetic beam is directed onto the preformed solder balls to melt them and fuse them to the contact pads.

Abstract: A method is disclosed for identifying regions of an integrated circuit layout design where optical proximity correction will be most useful and then performing optical proximity correction on those regions only. More specifically, the method includes the following steps: (a) analyzing an integrated circuit layout design with a design rule checker to locate features of the integrated circuit layout design meeting predefined criteria; and (b) performing optical proximity correction on the features meeting the criteria in order to generate a reticle design. The criteria employed by the design rule checker to select features include outside corners on patterns, inside corners on features, feature size, feature shape, and feature angles.

Abstract: An improved DBS receiver front end architecture having a voltage controlled oscillator for frequency synthesis. The voltage controlled oscillator includes a tank circuit having an adjustable resonance frequency which may be varied over an octave. A tuning oscillator drives the tank circuit and provides a signal having that resonance frequency to a range extender which provides a tuning frequency. When enabled, the range extender doubles the input frequency, and when disabled, simply passes the input frequency through. A feedback path provides a control voltage to the tank circuit to adjust the resonance frequency and thereby cause the tuning frequency to be a multiple of a reference frequency. The range extender extends the tuning frequency range over two octaves without a loss of frequency resolution. Broadly speaking, the present invention contemplates a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip.

Abstract: Rapid Thermal Processing of a semiconductor wafer is performed by scanning a laser beam across a silicon dioxide film in contact with a surface of the wafer. The silicon dioxide film absorbs the energy from the laser beam and converts the energy to heat. The heat, in turn, is transferred to the wafer. Temperature feedback can be obtained to increase control and uniformity of temperatures across the wafer.

Abstract: An on-chip misalignment indicator for measuring misalignment between layers of an integrated circuit die employs a first contact, and a second contact. A current path between the first and second contacts has a resistance that varies as a function of misalignment between successive layers of the integrated circuit die. Similarly, a method for detecting misalignment between layers of an integrated circuit die involves passing and measuring a current between a first contact and a second contact. The amount of the current is indicative of an amount of misalignment between layers of the integrated circuit die.

Abstract: Signal area efficiency in integrated circuit designs is improved by increasing the information efficiency of signal wiring on an integrated circuit. Candidate signals are selected for combination by prioritizing signals according to length of travel, travel path, and information content. Signals with low information content and with greater distance between endpoints make poor utilization of fixed wiring and provide the best candidates for improvement. Candidate signals which travel similar (substantially parallel) paths from point to point across the integrated circuit are combined to improve chip area utilization efficiency. A variety of techniques are described for combining low-information-content signals onto a small number of wires, transmitting them over the small number of wires, and re-expanding them at their destination. Assuming that the combining/expanding circuitry occupies less space than the point-to-point wiring which would otherwise be required, there is a net reduction in chip area.

Abstract: A test reticle and alignment mark optimization method is provided for determining the optimal alignment mark size for the efficient and accurate alignment of process layers during integrated circuit manufacture. The test reticle includes a number of orthogonally arranged alignment marks of various types and sizes and one or more registration structures. The method involves the steps of determining an initial expected range of alignment mark sizes on the test reticle which are suitable for a particular application; applying the test reticle patter to test wafers; further processing the test wafers; measuring the alignment signals produced by scanning the alignment marks in the initial expected range; quantifying the alignment signal quality; and fitting the quantified alignment signal quality to a statistical model to determine a range of optimal alignment signal dimensions.

Abstract: An encapsulated semiconductor package assembly including a substrate, a die operatively disposed on the substrate, a lid for support by the substrate over the die, a heat sink operatively on the lid and a releasable clip which clips the heat sink releasably to the lid. With the encapsulant over the die but not yet solidified, the lid is pressed down into the encapsulant and onto the substrate. Thereby when the encapsulant is cured the lid is held in place on the substrate. The clip clips onto a lip or a slot of the lid to releasably hold a heat sink on the lid for dissipating heat from the die. The lip can be formed by an overhanging portion of the lid, and the slot can be formed in a side wall of the lid.

Abstract: A computer-based system and method automate the generation of megacells in the design and layout of integrated circuits. The preferred method utilizes an automatic design generator having a user interface which receives design requirements for a megacell or other complex integrated circuit design. A megacell processor receives the design requirements for the megacell and retrieves relevant megacell implementations from a megacell library. Stored megacell benchmarks are then retrieved from a megacell benchmark memory and applied to corresponding megacells to determine which of the various implementations optimally satisfies the user design requirements. Once the optimal megacell implementation is selected, the megacell processor produces a logic design consisting of a net list and a physical design consisting of design directives which are then used to place and route the megacell as a finished layout.

Abstract: A Tape-Automated-Bonding (TAB) package includes a resilient polyimide layer that supports a metal leadframe. A microelectronic circuit die is mounted in a hole in the polyimide layer and interconnected with inner leads of the leadframe. The TAB package is adhered to a support member having spacers that abut against the surface of a printed circuit board (PCB) on which the package is to be mounted and provide a predetermined spacing between the leadframe and the surface. Outer leads that protrude from the leadframe are bent into a shape so as extend, in their free state, toward the surface at least as far as the spacers. The package and support member assembly is placed on the PCB surface, and the combination of the weight of the assembly, the resilience of the leads and the preset standoff height enable the leads to resiliently deform so that the spacers abut against the surface and the leads conformably engage with the surface for soldering or other ohmic connection to conjugate bonding pads on the surface.

Abstract: A thin dielectric substrate bearing a plurality of conductive leads has a hole circumscribed by the substrate in which is positioned a die having pads that are bonded to ends of leads carried by the substrate and projecting into the hole for contact with the die pads. The leads include free outer ends that project laterally outwardly and downwardly away from the plane of the substrate for connection to contact pads on a circuit board. The free leads are isolated from pressure applied to the chip on tape assembly after it has been connected to a circuit board by means of a thin self-supporting thermally conductive heat spreader that contacts the side of the die opposite its pads and includes fixed standoff and/or alignment pins that extend through alignment holes in the thin substrate and are in physical contact with a surf ace of the printed circuit board.

Abstract: A method for planning floor allocation of an integrated circuit to each function is disclosed. To provide enough core space to each of the functions and to meet some cost functions such as space utilization requirement of each of the functions, the disclosed method divides the core space to a grid of elementary regions. Then, pieces of the core space are defined and the pieces containing the borders and the overlapping areas of the functions are identified. Then, the identified pieces are used shift the allocated capacities of the functions as to shift excess capacity or core space from the functions with excess capacity to the functions with a shortage of capacity.

Abstract: A method is provided for generating test vectors to detect bridge faults in a semiconductor device. In one version of the invention, the method includes the steps of creating a net name data structure from a structural description of the semiconductor device which includes data representing the instance names for the nets to be tested, identifying a pair of nets in the net name data structure, and generating at least one test vector for the pair of nets such that, when the vectors impress on the nets, the state of the nets of the pair will change relative to each other such that logic, coupled to the pair, produces a signal which indicates whether a bridge fault exists between the nets of the pair.

Abstract: A functional test on a memory array, formed by a plurality of embedded memory segments each with a reprogrammable address, is conducted by programming the same address into each segment and conducting a portion of the functional test while simultaneously addressing all of the segments using the same reprogrammed address. A test pattern of signals is written into the segments by using the same reprogrammed address, and then unique addresses are reprogrammed after writing the test pattern signals. The signals which were created by writing the test pattern are read by using the unique addresses. The functional test is simplified by using the same address to write the test pattern, rather than generating unique addresses to write the test pattern to all of the memory segments.

Abstract: A local area interconnect structure comprising one or more electrically conductive interconnects formed from electrically conductive metal compounds is described and a process for forming same. Electrically conductive metal compounds are selectively deposited in one or more trenches which were previously formed in an insulation layer in a configuration conforming to the desired pattern of the electrically conductive interconnects. A seed layer is first selectively formed on surfaces of the trenches and the electrically conductive metal compound is then selectively deposited over the seed layer in the trench, but not on the exposed surfaces of the insulation layer.

Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates.

Abstract: Methods and associated apparatus for maintaining management information pertaining to a storage subsystem attached to a plurality of host systems. In particular, the present invention stores configuration and other management information regarding a storage subsystem in a reserved area of the storage subsystem called a host store region (HSR). The configuration information is timestamped by the storage subsystem when stored in the HSR. The information written therein is written and read by attached host systems using standard read and write commands directed specifically to the HSR. The storage subsystem has a reserved area distinct from the storage capacity used for persistent storage of host supplied data. A portion (the HSR) of this reserved area is set aside as a scratchpad for use by all attached host systems to communicate management information among one another. The present invention uses the existing communication channel between each of the attached host systems and the common storage subsystem.

Abstract: A character programming method (10) whereby a synchronization character (17) can be determined in a determine encoding scheme operation (12) and a determine synchronization character operation (14). The synchronization character (17) can then be programmed into a synch character logic (26) of an integrated circuit (20) or a core (20) thereof. The synch character logic (26) can be programmed through a plurality of program pins (30) on the periphery of the integrated circuit (20) or by more sophisticated means such as by sending the programming from a sending integrated circuit (40) to a receiving integrated circuit (42) through a communications line (44).