Abstract: An electrostatic discharge (ESD) protection circuit includes first and second supply terminals, a current source, a shunt transistor, an inverter and a voltage level shifting device. The shunt transistor is coupled between the first and second supply terminals and has a control terminal. The inverter includes an input coupled to the current source, an output coupled to the control terminal of the shunt transistor and pull-up and pull-down transistors coupled between the first and second supply terminals. The pull-up and pull-down transistors have control terminals which are coupled to the input. The voltage level shifting device is coupled between the input and the control terminal of one of the pull-up and pull-down transistors.

Abstract: An interposer (preformed planar structure) is disposed between a die and a substrate (which may be another die). Through holes in the interposer facilitate controlled formation of electrical connections between the die and the substrate. In one embodiment, the through-holes in the interposer are filled flush with a resilient plastic conductive material and pressed against raised conductive structures on the die and substrate. The die, interposer, and substrate are maintained in electrical contact under compression. The compressing force can be removed to replace the die. In another embodiment, the interposer has embedded conductive elements which make contact with selected connections between the die and the substrate. Electrical connections between the conductive elements can be selectively effected to provide for "re-wiring" of connections to the die and substrate.

Abstract: A random verification environment for verifying a semiconductor device includes a hardware engine programmed to include a random input generator that builds a set of test vectors. A first memory connected between the hardware engine and the semiconductor device stores the set of test vectors and supplies the set of vectors to the semiconductor device under the control of a first state machine generated by the hardware device. A second memory connected to the semiconductor device receives output signals from the semiconductor device in response to input test vectors. A random test iterator in the hardware engine provides a first state machine and also provides a second state machine that writes the signals output from the semiconductor device to the second memory. The test vectors are input to the semiconductor device at a rate equal to the operating rate of the semiconductor device. An expected output generator is arranged to receive the test vectors from the first memory.

Abstract: A system and method for using a BIST generator and a BIST compactor to characterize the propagation delay time of a high-speed embedded cores and integrated circuits in general. In one embodiment, an external clock is provided having a positive edge and a negative edge. The BIST generator and test compactor is configured to apply a set of test inputs to the integrated circuit in response to the positive edge, and the BIST compactor is configured to latch a set of outputs from the integrated circuit in response to the negative edge, and determine if the set of outputs represent a valid test result. The validity determination is monitored, and as long as the test result is valid, it is determined that the propagation delay time is less than the time interval between the positive and negative transitions. The propagation delay time can then be measured by reducing the time interval until invalid test results appear.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: An electronic system utilizing at least one integrated circuit including a semiconductor integrated circuit chip housed in a package providing external electrical connections for the circuit chip. The system package has only a limited number of external connections available for such use. The system package includes an internal buss, or plurality of busses, which are electrically connected to the circuit chip and to selected external connections or the package to improve the efficiency of utilization of external connections on the package, as well as improving operating characteristics of the integrated circuit chip by improvements to voltage and current distributions to the chip, and also eliminating in some cases the consequences of a poor quality of external electrical connection to the system package itself.

Abstract: Disclosed is a reusable hardware layout ("core") for performing some, but not all, MPEG-2 video decoding functions. The information content of the core may be stored on a machine readable media and includes a series of hardware layouts specifying the locations and features of various circuit elements comprising the video core architecture. The disclosed video decoder core design specifies that at least the following MPEG-2 functions are performed by the hardware: inverse scan, inverse quantization, inverse discrete cosine transform, half pel compensation, and merge. Other MPEG-2 functions such as motion vector decoding, variable length decoding, and run level decoding are not performed by hardware video cores fabricated in accordance with video core design.

Abstract: An improved DBS receiver front end architecture having a tuner chip and a demodulator/decoder chip. The tuner chip has reduced-power features which allow the incorporation of an on-chip voltage regulator. The tuner chip is a direct conversion tuner with on-chip tuning frequency generation and reduced power interface signals. The on-chip voltage regulator provides a constant power supply for nonlinear components of the tuner and frequency generation circuitry to minimize phase noise. Broadly speaking, the present invention concerns a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip. The tuner chip includes an on-chip voltage regulator, in addition to a tuning oscillator, a charge pump, a downconverter, and a lowpass filter. The on-chip voltage regulator is operable to provide a stable power supply to the tuning oscillator and the charge pump.

Abstract: An MPEG decoder system and method for decoding frames of a video sequence. The MPEG decoder includes frame reconstruction or decoder logic which operates to reconstruct a bi-directionally encoded (B) frame with minimal memory requirements. The MPEG decoder operates to decode or reconstruct the frame twice, once during each field display period. The picture reconstruction unit operates to decode or reconstruct the B frame twice, once each during a first field time and a second field time. The first field time substantially corresponds to the time when the first or top field of the picture is displayed, and the second field time substantially corresponds to the time when the second or bottom field of the picture is displayed. This obviates the necessity of storing the reconstructed B frame data, thus reducing memory requirements.

Abstract: A polishing apparatus and method is disclosed, whereby fluid is delivered at dissimilar flow rates and pressures across a wafer. The fluid is delivered either directly to the wafer or through a polishing pad. Changing the fluid delivery allows the removal properties of the fluid to polish material from the wafer surface based on the location of that material relative to the center of the wafer. The fluid delivery system and the polishing pad oscillate relative to a rotating wafer. The radius of oscillation is relatively small compared to the size of the wafer to allow removal along one or more concentric rings and/or circles across the wafer.

Abstract: A method, and resulting product, are disclosed for selectively forming polycrystalline silicon over exposed portions of a single crystal silicon substrate. The method includes inhibiting the formation of such polycrystalline silicon over adjacent silicon oxide surfaces; and the resulting product of such a process. The polycrystalline silicon is selectively deposited over the single crystal silicon substrate by first forming a thin layer of a lattice mismatched material over the single crystal silicon surface, and then depositing a layer of polycrystalline silicon over the lattice mismatched material. Preferably, the thin lattice mismatched layer comprises a silicon/germanium (SiGe) alloy.

Abstract: A plurality of devices communicate information over a wireless network at radio frequencies. The information includes digital audio, video and data. Bandwidth among the devices is dynamically allocated, the allocation being based upon the needs of the devices. One embodiment of the wireless network is a Time Division Multiple Access network. Another embodiment is a wireless Ethernet. Yet another embodiment is a Frequency Division Multiplexed network.

Abstract: An instruction swap is implemented in a dual pipelined microprocessor to make instruction flow smoother upon resource or structural conflicts in executing an instruction. Instructions are accessed in an even and odd pair with an even instruction proceeding an odd instruction. The accessed instructions are stored in Read/Decode registers for decoding and execution. The even and odd instructions are swapped in the registers and in execution when the preceding even instruction encounters an execution conflict or a branch.

Abstract: A method and apparatus for dissipating heat from a semiconductor device. A heat sink embodying the method includes an exterior surface contoured to better facilitate heat dissipation and/or direct a flow of air or fluid over the heat sink. In one embodiment, the heat sink includes a heat sink layer formed from a powdered metal. In another embodiment, the heat sink layer is contoured with a selected combination of bumps, indentations and holes. In yet another embodiment, the heat sink includes a stack of such heat sink layers which are mechanically interfitted and thermally coupled.

Abstract: This invention concerns a novel Viterbi decoding apparatus and method in which a novel survivor weight unit (SWU) implements a normalized survivor weight calculation method with permutations. This method permutes a vector of survivor weights in a manner which permits calculation of weights by specialized dual add-compare-select units. The specialization of the butterfly computation unit allows for a reduction of storage and computation requirements.

Abstract: A single leadframe package having stacked integrated chips mounted therein provides multiple electrical functions. The leadframe package construction includes a leadframe die having a substantially smaller outer peripheral dimension than a first integrated circuit chip mounted face down thereon for supporting from below the first integrated chip without obstructing its bond pads. A second integrated circuit is supported from below in a backside to backside configuration by the first integrated circuit without obstructing the bond pads of the second integrated circuit. A plurality of substantially short conductive wires interconnect electrically the first and second integrated circuit chips with selective ones of a plurality of leadframe conductors. An encapsulating material molds the construction into the single leadframe package.

Abstract: An integrated circuit structure with input/output gate voltage regulation and parasitic zener and junction diodes for protection against damage resulting from electrostatic discharge (ESD) events. The circuit includes a first protective FET connected between an input/output pad and a ground potential of the integrated circuit. A diode voltage regulator is also connected between the gate of the first protective FET and a reference potential of the integrated circuit. The first protective FET receives a voltage from its gate-drain overlap capacitance during an ESD event. The diode is operative during an ESD event to provide a sufficient voltage to the first FET gate to permit a desired ESD current flow through the first protective FET. In one embodiment the first FET is an NMOS device and the diode voltage regulator is a series of p-n forward biased diodes.

Abstract: Disclosed is a partitioning procedure for designing MPEG decoders, AC-3 decoders, and decoders for other audio/video standards. The procedure provides that some specified decoding functionality be implemented exclusively in the form of hardware and certain other specified decoding functionality be provided exclusively as firmware or software. A video decoder designed according to this procedure includes the following elements: (a) firmware or software for implementing, in conjunction with a CPU, video header processing functions; and (b) hardware for implementing preparsing assist, macroblock reconstruction, and video display control functions. An audio decoder designed according to this procedure includes the following elements: (a) firmware or software for implementing, in conjunction with a CPU, decoding fields containing parameters for processing the audio data; and (b) hardware for implementing matrixing and windowing functions on the audio data.

Abstract: Improved manufacturability, yield, and reliability are achieved during wirebonding of a semiconductor die of reduced size by employing two rows of staggered conductive connectors, or bond pads, for wirebonding the die to a semiconductor package. An outer row of conductive connectors is positioned closer to the edge of the die than an inner row of conductive connectors and includes a greater number of connectors than the inner row. The die can be wirebonded to a package substrate having either a single row of bondfingers or multiple rows of bondfingers. In one embodiment, bond wires attaching the inner row of conductive pad connectors to the package substrate have a greater loop height than bond wires attaching the outer row of conductive pad connectors to the package substrate.

Abstract: A physical design automation system for producing a highest fitness cell placement for an integrated circuit chip includes a decomposition/recomposition processor for decomposing a cell placement optimization process into a plurality of tasks and recomposing the highest fitness cell placement from results of performing the tasks. A plurality of worker processors independently perform the tasks and produce results. A host processor distributively assigns the tasks to the worker processors in response to work requests received therefrom. Each worker processor sends a work request to the host processor after completing a task. The host processor maintains a list of unassigned tasks, assigned tasks and completed tasks, and revises the list to redesignate assigned tasks as unassigned tasks upon determining that the list includes no unassigned tasks and at least one assigned task, thus making the system immune to the failure of one or more processors.